• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

• Journal of the Korean Society of Costume
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• v.58 no.7
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• pp.119-132
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• 2008

This study intended to develop and produce a modern form of fashion design for the Korean creative dance performance, 'Crazy Skirt Collage', which expressed conflict between internal ego and a persona in a woman. The qualitative method was used to analyze literature review, internet search and visual data of historically important cases related to the theme. Based on the analysis, the fashion design of the dance performanre by Hwang Hee-Yeon that was actually staged on Towol Theater, one of the Seoul Arts Center, was produced. The results wire as follows; First, the study confirmed a change of persona that revealed a female's animus strongly as it moved into the modern time. Second, the female's persona was expressed through long skirts, slips, dress shoes, handbags, military shoes, dresses with long zippers, trousers, wedding dresses and Korean full skirts during the performance, while the female's animus through male coats, panties, big bags and clock. In conclusion, it is necessary to study new expressive methods, that is, dance clothes using advanced equipment such as lights, videos or other variety of materials. It is also important to understand aesthetics of modern women's ordinary lives and to adapt ordinary clothes to dance clothes in various methods in order to express their modern lives appropriately through Korean creative dance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.25-34
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• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

• Aerospace Engineering and Technology
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• v.8 no.2
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• pp.92-97
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• 2009

Two conventional speed detection methods (Elapsed-time method and Pulse-count method) are analyzed and compared for a high speed motor with digital tacho pulse with non-uniformity. In general, the elapsed-time method usually has better performance than a pulse-count method in case sufficiently high speed clock is used to measure the time difference. But if a tacho pulse non-uniformity exists in the reaction wheel - most of reaction wheel has a certain amount of non-uniformity - the accuracy of the elapsed-time method is degraded significantly. Thus the performance degradation is analyzed with respect to the level of non-uniformity of tacho pulse distribution and an allowable bound is suggested.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2388-2404
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• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.3
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1605-1614
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• 2008

This paper proposed a new VLSI architecture of motion estimation (ME) and compensation (MC) for efficient video compression and implemented it to hardware. ME is generally calculated using SAD result. So we proposed a new arithmetic method for SAD. The proposed SAD calculation method increases arithmetic efficiency and decreases external memory usage. Finally it increases performance of ME/MC. The proposed ME/MC hardware was implemented to ASIC with TSMC 90nm HVT CMOS library. The implemented hardware occupies about 330K gates and stably operates the clock frequency of 143MHz.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.