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http://dx.doi.org/10.9766/KIMST.2016.19.3.379

Phase Noise Analysis of 2.4 GHz PLL using SPD  

Chae, Myeoung-ho (The 2nd Research and Development Institute, Agency for Defence Development)
Kim, Jee-heung (Electronic Warfare PMO, Agency for Defense Development)
Park, Beom-jun (Electronic Warfare PMO, Agency for Defense Development)
Lee, Kyu-song (Electronic Warfare PMO, Agency for Defense Development)
Publication Information
Journal of the Korea Institute of Military Science and Technology / v.19, no.3, 2016 , pp. 379-386 More about this Journal
Abstract
In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.
Keywords
Fixed PLL; SPD; Phase Noise; Loop Filter;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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