• 한국우주과학회:학술대회논문집(한국우주과학회보)
• /
• 한국우주과학회 2000년도 한국우주과학회보 제9권2호
• /
• pp.28-28
• /
• 2000

• 천문학논총
• /
• 제21권2호
• /
• pp.67-74
• /
• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• 전자공학회논문지C
• /
• 제34C권6호
• /
• pp.37-43
• /
• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• 전기학회논문지
• /
• 제61권10호
• /
• pp.1483-1488
• /
• 2012

This paper analyzed the precision and accuracy of the altitude-aided GNSS using the altitude information from digital map. The precision of altitude-aided GNSS is analysed using the theoretically derived DOP. It is confirmed that the precision of altitude-aided GNSS is superior to the general 3D positioning method. It is also shown that the DOP of altitude-aided GNSS is independent of altitude bias error while the accuracy was influenced by the altitude bias error. Furthermore, it is shown that, since the altitude bias error influenced differently to each pseudorange measurement, the effect of the altitude bias error is more serious than clock bias error which does not influence position error at all. The results are evaluated by the simulation using the commercial RF simulator and GPS receiver. It confirmed that altitude-aided GNSS could improve not only precision but also accuracy if the altitude bias error are small. These results are expected to be easily applied for the performance improvement to the land and maritime applications.

• 전기학회논문지
• /
• 제67권4호
• /
• pp.538-542
• /
• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• 한국항행학회논문지
• /
• 제13권2호
• /
• pp.178-186
• /
• 2009

SBAS(Satellite Based Augmentation System) 시스템에서는 GNSS 사용자들의 위치 정확도 향상을 위해 위성궤도 및 시계보정정보를 제공하고 있는데, 본 논문에서는 이러한 보정정보의 정확도에 대해 분석하였다. IGS(International GNSS Service)에서 제공하는 GPS 위성의 정밀궤도력을 참값으로 가정하고, 그에 대한 오차를 이용하여 정확도를 분석/수행하였다. 이때 IGS 정밀궤도력과의 정확한 비교를 위해 GPS 위성에 대한 안테나 위상중심 편차와 P1-C1 편이를 고려하였다. SBAS 위성궤도 및 시계보정 정보로는 미국의 WAAS와 일본의 MSAS 보정정보를 이용하였다. 정확도 분석을 통해 SBAS에서 제공하는 위성궤도 보정정보와 위성시계 보정정보가 상당한 상관관계를 가지고 있음을 확인하였다. 또한 보정정보의 정확도는 SBAS 시스템의 지상 네트워크 크기와 위성의 궤적에 영향을 받는 것을 확인하였다.

• Progress in Superconductivity
• /
• 제4권2호
• /
• pp.127-131
• /
• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• 한국통신학회논문지
• /
• 제21권5호
• /
• pp.1325-1331
• /
• 1996

본 논문에서는 전류 스위칭(switched-current:SI) 시스템에서 THD(total harmonic distortion) 증가 원인인 클럭피드스루(clock feedthrough:CFT) 오차 전압을 감소시키는 새로운 전류 메모리(current-memory) 회로를 제안하였다. 제안한 전류 메모리는 CMOS 상보형의 PMOS 트랜지스터를 이용하여 CFT 오차 전압에 의한 출력 왜곡 전류를 감소시킨다. 제안한 전류 메모리 회로를 $1.2{\mu}{\textrm{m}}$ CMOS 공정을 사용하여 설계하고, 입력으로 전류 크기 $68{\mu}{\textrm{m}}$인 1MHz 정현파 신호를 인가하였다.(샘플링 주파수:20MHz) 모의 실험 결과, 기존의 전류 메모리보다 CFT 오차 전압에 의한 출력 왜곡 전류가 10배 정도 감소를 나타내었으며 신호 대 바이어스 전류비가 0.5(peak signal-to-bias current ratio:i/J)인 1KHz 신호를 인가할 경우 THD는 -57dB이다.

• 제어로봇시스템학회논문지
• /
• 제7권6호
• /
• pp.550-557
• /
• 2001

There are several applications and error analysis methods using GPS(Global Positioning System) In most analysis positioning and timing errors are represented as the multiplication of DOP(Dilution Of Precision) and measurement errors, which are affected by the receiver and measurement type. Therefore, lots of DOPs are defined and used to analyze and predict the performance of positioning and timing systems. In this paper, the relationships between these DOPs are investigated in detail, The relationships between GDOP(Geometric DOP), PDOP(Position DOP) and TDOP(Time DOP) in the absolute positioning are de-rived. Using these relationships, the affect of clock bias is analyzed. The relationships between RGDOP(Relative DOP) and PDOP are also derived in relative positioning where the single difference and double dif-ference techniques are used. From the results, it is expected that using the common clock will give better performance when the single difference technique is used while the effects of clock is eliminate when the double difference technique is used. Finally, the error analyses of dual frequency receivers show that the narrow lane measurements give more accurate results than wide line of or L1. L2 independent measurements.

• 전자공학회논문지SC
• /
• 제46권2호
• /
• pp.72-77
• /
• 2009

본 논문은 별도 기준 클록 없이 고속 시리얼 데이터 통신을 위한 3.2Gb/s 클록 데이터 복원(CDR) 회로를 설명한다. CDR회로는 전체적으로 5부분으로 구성되며, 위상검출기(PD)와 주파수 검출기(FD), 다중 위상 전압 제어 발진기(VCO), 전하펌프(CP), 외부 루프필터(LF)로 구성되어 있다. CDR회로는 half-rate bang-bang 타입의 위상 검출기와 입력 pull-in 범위를 늘릴 수 있도록 half-rate 주파수 검출기를 적용하였다. VCO는 4단의 차동 지연단(delay cell)으로 구성되어 있으며 튜닝 범위와 선형성 향상을 위해 rail-to-rail 전류 바이어스단을 적용하였다 각 지연단은 풀 스윙과 듀티의 부정합을 보상할 수 있는 출력 버퍼를 갖고 있다. 구현한 CDR회로는 별도의 기준 클록 없이 넓은 pull-in 범위를 확보할 수 있으며 기준 클록 생성을 위한 부가적인 Phase-Locked Loop를 필요치 않기 때문에 칩의 면적과 전력소비를 효과적으로 줄일 수 있다. 본 CDR 회로는 0.18um 1P6M CMOS 공정을 이용하여 제작하였고 루프 필터를 제외한 전체 칩 면적은 $1{\times}1mm^2$이다. 3.2Gb/s 입력 데이터 율에서 모의실험을 통한 복원된 클록의 pk-pk 지터는 26ps이며 1.8V 전원전압에서 전체 전력소모는 63mW로 나타났다. 동일한 입력 데이터 율에서 테스트를 통한 pk-pk 지터 결과는 55ps였으며 신뢰할 수 있는 입력 데이터율 범위는 약 2.4Gb/s에서 3.4Gb/s로 나타났다.