• Korean Journal of Optics and Photonics
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• v.11 no.3
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• pp.166-170
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• 2000

A wavelength tunable all-optical clock recovery using a semiconductor optical amplifier in a fiber ring cavity is proposed and demonstrated at the wavelength of 1530 nm to 1570 nm. A synchronized optical pulse train is recovered from 10 Gbps and 30 Gbps randomly generated optical pulse streams with injection locking technique. Also, the system responses to the perturbation and the input average power variation are analyzed by a large-signal model based on time-domain travelling wave equation. ation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.149-152
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• 1998

A synchronization is very important element not only wire communication but also wireless communication. A synchronous oscillator(SO) is a network which synchronizes, tracks, filter, amplifies and divides (if necessary) in a single process. The coherent phase synchronous oscillator(CPSO) is created by adding two external loops to the SO. The CPSO ratains all virtues of a SO while providing coherency throughout the tracking range. This paper has applied a clock recovery of GPS signal using CPSO.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.10-14
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• 1987

Considering transition gating of the input unipolar NRZ signal, the equivalent linear time-invariant model has been derived for the PLL in the timing clock recovery circuits. The magnitude of the alignment and accumulated jitter has been found along a chain of repeaters. For the timing recovery circuit of 90 Mbps optical communication system, the computer simulation shows that, for the first stage of the chain, the alignment jiter and the accumulated jitter are of -5.1766 dB and for the 7-th stage, the alignment jitter and accumulated jitter have the value of -1.0193dB, 4.9053 dB respectively.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.29-36
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• 2005

All-optical fiber-type $2{\times}32$ splitters for an Ethernet PON (passive optical network) were fabricated by using a FBT (fiber biconical tapered) process and the performance of the splitters was tested in upstream transmission of the EPON system. The $2{\times}32$ splitters was obtained by cascading $1{\times}4$ splitters fabricated by a conventional FBT process and showed -18 dB of insertion loss with 1.5 dB uniformity of output power at each channel and -0.1 dB of polarization dependent loss. The insertion loss variation was below 0.1 dB at the temperature range of $-40^{\circ}C\;to\;80^{\circ}C$. For upstream channel transmission test in the EPON system were a Zig board and a burst mode receiver. Zenko-made optical module was used for the burst mode receiver by adding functions of serializer/deserializer and clock data recovery, a Virtex II pro20 chipset and Vitesse VSC7123 were used in the Zig board for characterizing the burst mode and in the clock data recovery chipset, respectively. Startup acquisition lock time and data acquisition lock time were measured to be 670ns and 400ns, respectively, in the upstream channel transmission of the EPON system adapting the $2{\times}32$ splitter fabricated in this work.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.9-18
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• 2008

Recently according to the development of an information society the information technology equipments which a clock frequency has the facility over a number giga hertz have been developed much. And we have research which leakage electromagnetic signals can use at the communication security and tapping. In this paper, we restored leakage electromagnetic signals of the monitors. And we proposed efficient recovery technique to restore the screen of the monitor. First of all, we understand a screen characteristic of the monitor. And then we restored a monitor screen from leakage electromagnetic signals from the monitor. For also we tried to use a Wavelet transform and filters to remove the noise for better performance. In the result of the experiment, we used leakage electromagnetic signals and confirmed the possibility of a monitor screen of the recovery. And we improve the performance with Wavelet transform and filters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.337-343
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• 2009

In this paper, we proposed a burst mode symbol timing recovery unit that is applicable to the VDL Mode-2 using D8PSK modulation. A method that IIR loop filter is used to minimize symbol timing error is hard to apply to burst mode because its convergence time is long. That is, the fast convergence property is important. In this paper, the proposed method takes one sample which has maximum symbol power after the initial synchronization has been achieved by using preambles. The main principle of operation is that the unit moves one sample clock to advance or retard according to symbol power. We verify that the proposed method is operated well in ${\pm}100$ ppm or greater through the test results between Australia ADS Corp. transmitter and the designed receiver.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.77-84
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• 2000

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.