• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• 한국전자파학회논문지
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• 제25권11호
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• pp.1190-1196
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• 2014

본 논문은 넓은 고도 범위와 낮은 측정 오차를 갖는 주파수 변조 연속파(FMCW) 레이더 고도계의 설계 방안을 제안한다. 측정 고도의 동적 범위를 줄이기 위해 전파 고도계의 송신 경로에 광 지연선을 적용하여 넓은 고도 범위를 얻을 수 있다. 송신 전력과 수신단 이득을 제어하여 또한 수신 전력의 동적 범위를 줄일 수 있다. 더불어, 직접 디지털 합성기를 사용하여 변조 선형성을 향상시키고, 기준 클럭 신호를 위상 고정 루프의 옵셋(offset) 주파수로 사용하여 위상잡음을 최소화함으로써 낮은 고도 측정오차를 갖는다.

• 한국통신학회논문지
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• 제28권2A호
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• pp.96-101
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• 2003

본 연구는wideband code division multiple access (WCDMA) 단말기 복조기의 주요 구성 요소인 time tracker의 구현과 설계 parameter 설정에 관한 것이다. Time tracker는 2차 feedback loop로 구성되었고 모의실험을 통하여time error detector (TED)의 이득을 기지국이 송출하는 전체 전력에서 CPICH 전력이 차지하는 비의 함수로 도출하였다. Loop filter, numerically controlled oscillator (NCO) 설계를 포함한 time tracker의 전달함수를 구하였다. 모의실험을 통하여 기지국과 단말 사이의 clock time offset, loop bandwidth를 매개변수로 하여 DPCH 전력에 따른 bit error rate (BER)를 구하였고 이를 근거로 통신 환경에 따라 설정해 주어야 할 적합한 이득 값을 제시하였다.

• ETRI Journal
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• 제26권6호
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• pp.657-660
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• 2004

We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• 전기학회논문지
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• 제57권6호
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.737-747
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• 2011

5678SMRT has installed various sensor for operating conditions(field of electric, facilities, signal, communication equipment and track) and environment of Every Function Room for remotely detecting and monitoring. Installed sound sensor for analyzed after remotely heard the noise of every equipment at Every Function Room and temperature sensor for check the temperature condition of Every Function Room. Additional installed voltage sensor in signal equipment room for monitoring RF track-circuit's voltage condition. Installed displacement sensor at The Chungdam bridge's railway for measuring and monitoring track displacement caused by temperature change and Pan/Tilt camera at sub-station and drainage for remotely field monitoring. Installed sensor for each equipment's operating condition and failure at Every Function Room then periodic check of workforce turned to around-the-clock surveillance by sensor therefore improvement of operating equipment. SMRT is lots of prevent a failure by Immediately detect of precondition of equipment failure by analyzed the sensor data. If the occurrence of an failure, become detected Immediately so possibility correct diagnosis and order by remotely field check by installed camera and sound sensor at field.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• 전기학회논문지P
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• 제62권2호
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• ETRI Journal
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• 제34권1호
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• pp.122-125
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• 2012

A video signal through a high-density optical link has been demonstrated to show the reliability of optical link for high-data-rate transmission. To reduce optical point-to-point links, an electrical link has been utilized for control and clock signaling. The latency and flicker with background noise occurred during the transferring of data across the optical link due to electrical-to-optical with optical-to-electrical conversions. The proposed synchronization technology combined with a flicker and denoising algorithm has given good results and can be applied in high-definition serial data interface (HD-SDI), ultra-HD-SDI, and HD multimedia interface transmission system applications.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.