• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Structural Engineering and Mechanics
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• v.73 no.4
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• pp.427-436
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• 2020

The use of final IGS precise orbit and clock products for high-rate GNSS-PPP proved its effectiveness in capturing dynamic displacement of engineering structures caused by earthquakes. However, the main drawback of using the final products is that they are available after approximately two weeks of data collection, which is not suitable for timely measures after an event. In this study, the use of ultra-rapid products (observed part), which are available after a few hours of data collection, and rapid products, which are available in less than 24 hrs, are investigated and their results are compared to the more precise final products. The tests are designed such that harmonic oscillations with different frequencies and amplitudes and ground motion of a simulated real earthquake are generated using a single axis shake table and the PPP was used to capture these movements by monitoring time-change of the table positions. To evaluate the accuracy of PPP using ultra-rapid, rapid and final products, their results were compared with relative GNSS positioning and LVDT (Linear Variable Differential Transformer) data, treated as reference. The results show that the high-rate GNSS-PPP solutions based on the three products can capture frequencies of harmonic oscillations and dynamic displacement with good accuracy. There were slight differences between ultra-rapid, rapid and final products, where some of the tested events indicated that the latter two produced are more accurate and provide better results compared to the ultra-rapid product for monitoring short-term dynamic displacements.

• Korean Journal of Optics and Photonics
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• v.10 no.2
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• pp.146-151
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• 1999

We demonstrated a harmonic mode locking scheme that used regeneratie phase modulation to get a high and stable repetition rate in a figure-of-eight fiber soliton laser. From the detected beat spectra of the laser output, a sinusoidal clock freguency tone of 400 MHz, the 96th harmonics of the fundamental mode locking frequency, was extracted with a high Q filter and was used to drive the phase modulator, resulting in stable output of soliton pulse train synchronized with the modulation signal. Generated soliton pulses had FWHM pulsewidth of 930 fs and 3.1 nm linewidth, yielding pulsewidth-bandwidth product of 0.359 that was close to the transform limit. As the modulation frequency always followed the beat frequency of laser modes, stable harmonic mode locking was achieved without the adjustment of the cavity length, which has been commonly required in actively mode-locked lasers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Structural Engineering and Mechanics
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• v.89 no.6
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• pp.589-599
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• 2024

This study presents the usability of the high-rate single-frequency Precise Point Positioning (SF-PPP) technique based on 20 Hz Global Positioning Systems (GPS)-only observations in detecting dynamic motions. SF-PPP solutions were obtained from post-mission and real-time GNSS corrections. These include the International GNSS Service (IGS)-Final, IGS real-time (RT), real-time MADOCA (Multi-GNSS Advanced Demonstration tool for Orbit and Clock Analysis), and real-time products from the Australian/New Zealand satellite-based augmentation systems (SBAS, known as SouthPAN). SF-PPP results were compared with LVDT (Linear Variable Differential Transformer) sensor and single-frequency relative positioning (SF-RP) solutions. The findings show that the SF-PPP technique successfully detects the harmonic motions, and the real-time products-based PPP solutions were as accurate as the final post-mission products. In the frequency domain, all GNSS-based methods evaluated in this contribution correctly detect the dominant frequency of short-term harmonic oscillations, while the differences in the amplitude values corresponding to the peak frequency do not exceed 1.1 mm. However, evaluations in the time domain show that SF-PPP needs high-pass filtering to detect accurate displacement since SF-PPP solutions include trends and low-frequency fluctuations, mainly due to atmospheric effects. Findings obtained in the time domain indicate that final, real-time, and MADOCA-based PPP results capture short-term dynamic behaviors with an accuracy ranging from 3.4 mm to 8.5 mm, and SBAS-based PPP solutions have several times higher RMSE values compared to other methods. However, after high-pass filtering, the accuracies obtained from PPP methods decreased to a few mm. The outcomes demonstrate the potential of the high-rate SF-PPP method to reliably monitor structural and earthquake-induced ground motions and vibration frequencies of structures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.991-997
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• 2013

A new frequency tuning scheme and a transconductor with a wide tuning range and low harmonic distortion is presented. This frequency tuning technique is based on the relationship between the time-constant and the elapsed times in charging a capacitor up to a certain level. Its structure is as simple as that of a conventional tuning scheme using a VCF(Voltage-Controlled Filter) and it does not need a pure sine wave but uses a CLK(Clock) pulse as a reference signal, which is easily obtained from on-chip system clocks or external X-tal oscillators. When a certain reference CLK is given, without complex capacitor arrays the pole frequency of the filter can be controlled continuously in the frequency domain. Simulation results are presented to confirm the operation of the proposed approach.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.55-61
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• 2013

In this paper, we describe design and implementation of audio encoder/decoder for voice synthesis. It uses the encoding of difference value of successive samples instead of the original sample value. and has the compression ratio of 4. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 16.384MHz. The measured THD+n is from -40dB to -80dB with frequency variation and the power consumption is about 80mW. It is suited for the mobile application of high audio quality and low power consumption.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.