• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2001년도 추계학술대회 논문집
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• pp.147-149
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• 2001

In order to understand the influence of the modification of deformation texture on the formation of annealing texture, the evolution of texture during the clock rolling and the subsequent annealing was investigated by employing X-ray texture measurements and microstructure observation. The $\beta$-fiber orientations were proved to be quite unstable during the clock rolling. The clock rolled texture having uniform orientation densities along $\{011\}//ND$ fiber resulted in the randomization of annealing texture. This indicated that the operation of both the oriented nucleation and the oriented growth was effectively suppressed in the clock-rolled specimen during recrystallization.

• ETRI Journal
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• 제30권3호
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• pp.461-468
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• 2008

This paper presents a chromatic dispersion monitoring technique using a clock-frequency component for carrier-suppressed return-to-zero (CSRZ) signal. The clock-frequency component is extracted by a clock-extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high-speed optical communication systems.

• 한국동물번식학회:학술대회논문집
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• 한국동물번식학회 2004년도 춘계학술발표대회
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• pp.261-261
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• 2004

Circadian rhythms, which measure time about 24 hours, are generated by one of the most ubiquitous and well investigated timing system. More recently, circadian clock gene expression has been reported in various peripheral tissues. If a circadian clock is functioning in the testis, expression of clock genes should be observed in this tissue. To resolve this issue, we examined the expression of circadian clock genes in the testis. (omitted)

• 한국전자통신학회논문지
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• 제2권3호
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• pp.163-167
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• 2007

본 논문에서는 전력 소비를 감소시킬 수 있는 클럭게이팅 기법을 제안하여 8bit RISC 마이크로프로세서를 설계하였다. 제안된 설계 방법의 타당성을 검토하기 위해서 저전력을 고려하지 않은 8비트 마이크로프로세서와 클록 게이팅을 이용한 저전력 8비트 마이크로프로세서를 설계하여 소모 전력을 비교하였다. 기존의 마이크로 프로세서와 저전력으로 설계된 마이크로프로세서와의 소모 전력을 비교한 결과 시간에 대하여 비교하였을 경우 동적 소모 전력에 대하여 21.56% 감소를 얻을 수 있었다.

• 센서학회지
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• 제26권6호
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• pp.408-413
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• 2017

In this paper, we newly developed a byte-inverted transmission method for flicker-free visible light communication (VLC). The VLC transmitter sends original data in the former half period of the clock, and inverted data and in the latter half period of the clock. The VLC receiver receives the original data in the in the former half period of the clock. In this system, we used 480Hz clock that was generated from the 60Hz power line. The average optical power of the LED array in the transmitter is constant, thus flicker-free, in the observation time longer than the period of the clock that is about 2ms. This period is shorter than the maximum flickering time period (MFTP) of 5ms that is generally considered to be safe. This configuration is very useful in constructing indoor wireless sensor networks using LED light because it is flicker-free and does not require additional transmission channel for clock transmission.

• 한국측량학회지
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• 제25권6_1호
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• pp.537-543
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• 2007

Since the GPS absolute positioning with pseudorange measurements can significantly be affected by the observation error, the time series analysis of the GPS receiver clock errors was performed in this study. From the estimated receiver clock errors, the time series model is generated, and constrained back in the absolute positioning process. One of the CORS (Continuously Operating Reference Stations) network is used to analyze the behavior of the receiver clock. The dominant part of the model is the linear trend during 24 hours, and the seasonal component is also estimated. After constraining the modeled receiver clock errors, the estimated position error compared to the published coordinates is improved from ${\pm}11.4\;m\;to\;{\pm}9.5\;m$ in 3D RMS.

• 디지털산업정보학회논문지
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• 제4권1호
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• pp.9-16
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• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• 한국정보통신학회논문지
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• 제1권2호
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• Journal of Electrical Engineering and Technology
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• 제8권4호
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• pp.773-779
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• 2013

We propose an efficient method to measure a pulse width using multiphase clock signals generated from a ring oscillator. These clocks, which have the same frequency and are evenly spaced, give multiple rising edges within a clock cycle. Thus, it is possible to measure a pulse width more accurately than with existing single clock-based methods. The proposed method is applied to a capacitive touch switch. Experimental results show that the capacitive touch switch with the proposed method gives a 118 fF resolution, which is 6.4 times higher than that of the touch switch with a single clock-based pulse width measurement method.