• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.37-42
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• 2007

Clock grid networks are now common in most high performance microprocessors. This paper presents a new effective modeling and simulation methodology for the clock grid using scattering parameter. It also shows the effect of wire width and grid size on the clock skew of the grid. The interconnection of the clock grid is modeled by RC passive elements. The results show that the error is within 10 % comparing to Hspice simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• Publications of The Korean Astronomical Society
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• v.28 no.2
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• pp.17-23
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• 2013

Song I-Yeong (1619 ~ 1692), who was an astronomy professor of Gwansanggam (觀象監, Bureau of Astronomy), created the Honcheonsigye (渾天時計, Armillary Clock) in 1669 (10th year of King Hyeonjong Era). Honcheonsigye was a unique astronomical clock which combined an armillary sphere, the traditional astronomical instrument of the Far East, with the power mechanism of western alarm clock. The clock part of this armillary clock is composed of two major parts which are the going-train, power unit used the weight, and the time signal system in a wooden case. The time signal system is composed of four parts which are the time-annunciator, the striking train, the 12 different time-announcing medallions and the sound bell. This clock has been neglected for many years and its several components have been lost. This study is to understand the structure of time signal system and suggests the restoration process.

• Journal of Life Science
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• v.27 no.10
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• pp.1225-1231
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• 2017

Disruptive expression patterns of the circadian clock genes are highly associated with many human diseases, including cancer. Cell cycle and proliferation is linked to a circadian rhythm; therefore, abnormal clock gene expression could result in tumorigenesis and malignant development. The molecular network of the circadian clock is based on transcriptional and translational feedback loops orchestrated by a variety of clock activators and clock repressors. The expression of 10~15% of the genome is controlled by the overall balance of circadian oscillation. Among the many clock genes, Period 1 (Per1) and Period 2 (Per2) are clock repressor genes that play an important role in the regulation of normal physiological rhythms. It has been reported that PER1 and PER2 are involved in the expression of cell cycle regulators including cyclins, cyclin-dependent kinases (CDKs), and CDK inhibitors. In addition, correlation of the down-regulation of PER1 and PER2 with development of many cancer types has been revealed. In this review, we focused on the molecular function of PER1 and PER2 in the circadian clock network and the transcriptional and translational targets of PER1 and PER2 involved in cell cycle and tumorigenesis. Moreover, we provide information suggesting that PER1 and PER2 could be promising therapeutic targets for cancer therapies and serve as potential prognostic markers for certain types of human cancers.

• The Journal of the Korea Contents Association
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• v.15 no.11
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• pp.313-321
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• 2015

To minimize CT examination for Hip FAI diagnosis and operation plan. also, whether the MRI 3D images can replace Hip Clock face image was evaluated when performing Hip FAI MRI by using additional 3D image. This study analyzed Hip MRI and 3D Hip CT images of 31 patients in this hospital. For the purpose of evaluating the images, one orthopedic surgeon and one radiology specialist reconstructed Clock face, at MR and CT modality, by superior 12 o'clock, labrum front 3 o'clock, and the other side 9 o'clock, centering on Hip joint articular transverse ligament 6 o'clock. Afterwards, by the Likert Scale 5 point scale (independent t-test p<0.005), this study evaluated the check-up of A. retinacular vessel, B. head neck junction at 11 o'clock, A. Epiphyseal line, B. Cam lesion at 12 o'clock, and Cam lesion, Posterior Cam lesion at 1,2,3 and 4 o'clock. As for the verification of reliability among observers, this study verified coincidence by Cohen's weighted Kappa verification. As a result of Likert scale for the purpose of qualitative evaluation about the image, 11 o'clock A. retinacular vessel MR average was $3.69{\pm}1.0$ and CT average was $2.8{\pm}0.78$. B. head neck juncton didn't have a difference between two observers (p <0.416). 12 o'clock A. Epiphyseal line MR average was $3.54{\pm}1.00$ and CT average was $4.5{\pm}0.62$(p<0.000). B. Cam lesion didn't have a difference between two observers (p <0.532). 1,2,3,4 Cam lesion and Posterior Cam lesion were not statistically significant (p <0.656, p <0.658). As a result of weighted Kappa verification, 11 o'clock A.retinacular vessel CT K value was 0.663 and the lowest conformity. As a result of coincidence evaluation on respective item, a very high result was drawn, and two observers showed high reliability.

• Journal of Photoscience
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• v.9 no.2
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• pp.25-28
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• 2002

The chicken pineal gland has been used for studies on the circadian clock, because it retains an intracellular phototransduction pathway regulating the phase of the intrinsic clock oscillator. Previously, we identified chicken clock genes expressed in the gland (cPer2, cPer3, cBmal1, cBmal2, cCry1, cCry2, and cClock), and showed that a cBMALl/2-cCLOCK heteromer acts as a regulator transactivating cPer2 gene through the CACGTG E-box element found in its promoter. Notably, mRNA expression of cPer2 gene is up-regulated by light as well as is driven by the circadian clock, implying that light-dependent clock resetting may involve the up-regulation of cPer2 gene. To explore the mechanism of light-dependent gene expression unidentified in animals, we first focused on pinopsin gene whose mRNA level is also up-regulated by light. A pinopsin promoter was isolated and analyzed by transcriptional assays using cultured chicken pineal cells, resulting in identification of an 18-bp light-responsive element that includes a CACGTG E-box sequence. We also investigated a role of mitogen-activated protein kinase (MAPK) in the clock resetting, especially in the E-box-dependent transcriptional regulation, because MAPK is phospholylated (activated) in a circadian manner and is rapidly dephosphorylated by light in the gland. Both pulldown analysis and kinase assay revealed that MAPK directly associates with BMAL1 to phosphorylate it at several Ser/Thr residues. Transcriptional analyses implied that the MAPK-mediated phosphorylation may negatively regulate the BMAL-CLOCK-dependent transactivation through the E-box. These results suggest that the CACGTG E-box serves not only as a clock-controlled element but also as a light-responsive element.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.