• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.4
• /
• pp.667-673
• /
• 2000

This paper presents the modeling method of nonlinear circuits with lumped elements by using a hybrid Haar -wavelet MRTD/FDTD techniques. To analyze nonlinear circuits with lumped elements, the Haar-wavelet MRTD scheme is applied to the entire structure of interest and the conventional FDTD scheme is locally used to describe the characteristics of the lumped elements. To validate the scheme, microstrip structure with lumped elements and a single diode mixer are simulated.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.3
• /
• pp.297-303
• /
• 2012

This paper presents the simulation results for the analysis of a lightning surge, switching transients and very fast transients within a thermal plant. The modeling of gas insulated substations (GIS) makes use of electrical equivalent circuits that are composed of lumped elements and distributed parameter lines. The system model also includes some generators, transformers, and low voltage circuits such as 24V DC rectifiers and control circuits. This paper shows the simulation results, via EMTP (Electro-Magnetic Transients Program), for three overvoltage types, such as transient overvoltages, switching transients, very fast transients and a lightning surge.

• Journal of Power Electronics
• /
• v.9 no.4
• /
• pp.567-574
• /
• 2009

A linear transfer function for the output current control of frequency-controlled resonant inverters is proposed in this paper. The circuit of resonant inverters can be transformed into two coupled circuits through the complex phasor transform. The circuits consist of cross-coupled power sources and passive elements. The circuits are used to induce the state space equation, which is transformed into the $4^{th}$ order cross-coupled transfer function. The $4^{th}$ order cross-coupled transfer function is modeled into a $2^{nd}$ order linear transfer function based on a behavior analysis of the pole and zero locations that facilitate a simple and intuitive linear transfer function. The feasibility and validity of the proposed linear transfer function were verified by simulation and experiment.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.1005-1008
• /
• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• Transactions on Electrical and Electronic Materials
• /
• v.12 no.1
• /
• pp.7-10
• /
• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.9
• /
• pp.38-48
• /
• 1998

Generating test patterns for asynchronous sequential circuits remains to be a very difficult problem. There are few algorithms for this problem, and previous works cut feedback loops, and insert synchronous flip-flops in the feedback loops during ATPG. The conventional algorithms are similar to the algorithms for synchronous sequential circuits. This means that the conventional algorithms generate test patterns by modeling asynchronous sequential circuits as synchronous sequential circuits. So, test patterns generated by those algorithms nay not detect target faults when the test patterns are applied to the asynchronous sequential circuit under test. In this paper an algorithm is presented to generate test patterns for asynchronous sequential circuits. Test patterns generated by the algorithm can detect target faults for asynchronous sequential circuits with the minimal possibility of critical race problem and oscillation. And it is guaranteed that the test patterns generated by the algorithm will detect target faults.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.7
• /
• pp.515-521
• /
• 2013

Magnetoelectric(ME) bulk composites with PZT-PNN-PZN/$Fe_2O_4$ were prepared by using a conventional ceramic methods and investigated on the ME voltage vs frequency of ac magnetic fields. We made the electric equivalent circuits by using the Maxwell-Wagner model and simulated the frequency dependence of ME voltage in low frequency region. ME devices were described by a series of two equivalent circuits of piezoelectric and magnetic, which have the relaxation time ${\tau}$ due to the interaction between ME device and load resistor. Equivalent circuit of piezoelectric material is independent of frequency. However ferrite magnetic materials have Debye absorption and dipolar dispersion, whose equivalent circuit is a function of frequency. Therefore we suggest the resistance in the equivalent circuit is proportion to $1+{\omega}^2{\tau}^2$ and the capacitance is in inverse proportion to $1+{\omega}^2{\tau}^2$ in the magnetic materials.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.512-515
• /
• 1991

The advantages of poly-phase converter are to be able to reduce the ripple current and to lessen the weight of power inductors. This paper is derived the equivalent circuit, dc of and ac modeling circuit of a 3-phase multiple buck converter by using state space representation and averaging techniche. Futhermore, it is represented the equivalent circuits according to the duty cycle.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.3
• /
• pp.189-192
• /
• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.367-374
• /
• 2016

This paper presents an electro-thermal modeling of an amorphous silicon (a-Si) uncooled microbolometer. This modeling provides a comprehensive solution for simulating the electro-thermal characteristics of the fabricated microbolometer and enables electro-thermal co-simulation between MEMS and CMOS integrated circuits. To validate this model, three types of uncooled microbolometers were fabricated using a post-CMOS surface micromachining process. The simulation results show a maximum discrepancy of 2.6% relative to the experimental results.