• Title/Summary/Keyword: Circuit simulation

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Computer Simulation of Plasma Flows in Switching Devices (전력용 차단장치의 플라즈마 유동에 관한 전산해석)

  • Lee, Jong-Chul;Kim, Chul-Soo;Heo, Joong-Sik;Kim, Youn-J.
    • Proceedings of the KIEE Conference
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    • 2006.07b
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    • pp.641-642
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    • 2006
  • The modelling of some different types of switchgears has been reported in the previous papers. This paper consists of two parts. The first part concerns the modelling and simulation of switching arcs with an auto-expansion circuit breaker as an example. The second part focuses on the simulation of the PTFE nozzle ablation effect with three different nozzle shapes. For circuit breakers, the modelling of moving contact and the choice of time steps are discussed before typical results are given and compared with available test result.

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A simulation of Lightning Performance of the 154 kV Transmission Line with the Surge Arrester Installation (154 kV 송전선로에 피뢰기 설치시 내뢰성 향상효과 모의)

  • Shim, Eung-Bo;Woo, Jung-Wook
    • Proceedings of the KIEE Conference
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    • 1997.07e
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    • pp.1642-1644
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    • 1997
  • The simulation study of lightning faults reducing effects by the installation of surge arresters on the 154 kV transmission line is stated here. For the purpose of detailed simulation of arcing horn, a flashover model with dynamic characteristics of arcing horn gap was represented as a non-linear inductance which is controlled by EMTP/TACS(Electromagnetic Transient Program/fransient Analysis of Control Systems) switches. The back flashover inducing current was increased from 50 kA to 88 kA by the installation of surge arresters on the transmission line which has one ground wire and 20 ohms of tower footing resistances. The great advantage of surge arrester installation on one circuit of the double circuit transmission line is to prevent the simultaneous back flashover up to 190 kA.

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A study on the method of efficient PCB assembly by separation of crowed area and double allocation of slot (밀집구역분리와 슬롯이중배정에 의한 효율적 PCB 조립 방법의 연구)

  • Moon, Gee-Ju;Chang, Jae-Hyuk
    • Journal of the Korea Society for Simulation
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    • v.14 no.2
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    • pp.25-34
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    • 2005
  • Determination of component mounting sequence on printed circuit board assembly process is a typical NP-hard problem. It is a kind of traveling salesman problems, but it has one more hard to meet constraint of matching component type per mounting position as well as searching the shortest path. An efficient method is developed by separation of crowed area and allowing up to two slots per component type. A simulation model is constructed using Visual C++ for evaluation of the suggested heuristic.

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A Fault Simulation Method Based on Primary Output (근본 출력에 근거한 고장 모의실험)

  • 이상설;박규호
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.6
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    • pp.63-70
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    • 1994
  • In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.

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Comparison of Various Methods to Mitigate the Flicker Level of DFIG in Considering the Effect of Grid Conditions

  • Kim, Yun-Seong;Marathe, Aditya;Won, Dong-Jun
    • Journal of Power Electronics
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    • v.9 no.4
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    • pp.612-622
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    • 2009
  • The short circuit ratio (SCR) of a given grid is able to show the stability of the system in the case of unwanted elements, such as wind turbulence. This paper presents the simulation of a model of the doubly fed induction generator in the simulation software PSCAD/EMTDC. This model has been used to study flicker during continuous operation and the effect of SCR and grid impedance angle on flicker emission. Simulation results show that compensation of the stator reactive power is an effective method to considerably reduce the flicker levels, irrespective of the grid conditions.

A Pspice Model with CCFL Ballast PFC using Piezoelectric Transformer (압전 변압기를 이용한 PFC CCFL 안정기의 PSPICE 모델)

  • Hwang, Lak-Hoon;Cho, Moon-Taek;Lee, Sang-Yong;Ryoo, Ju-Hyun;Kim, Ju-Rae;Kim, Jong-Sun;Yoo, Chung-Sik
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.1209-1211
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    • 2000
  • This paper presents a PSPICE circuit model for the simulation of both static and dynamic characteristics of fluorescent lamps. The model can by utilized for an electric ballast simulation with continuous dimming and transient mode simulation such as step dimming Characteristics of a Rosen-type piezoelectric transformer were analyzed by combining an equivalent circuit with piezoelectric equations and the relation between the characteristics and the dimension of the PT was studied.

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A Study on Pspice Modeling with CCFL using Piezoelectric Transformer (압전변압기를 이용한 CCFL의 PSPICE 모델링에 관한 연구)

  • Hwang Lak-Hoon;Kim Ju-Rae;Lee Sang-Yong;shin yang-ho;Cho Moon-Taek
    • Proceedings of the KIPE Conference
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    • 2001.07a
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    • pp.630-633
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    • 2001
  • This paper presents a PSPICE circuit model for the simulation of both static and dynamic characteristics of fluorescent lamps. The model can by utilized for an electric ballast simulation with continuous dimming and transient mode simulation such as step dimming Characteristics of a Rosen-type piezoelectric transformer were analyzed by combining an equivalent circuit with piezoelectric equations and the relation between the characteristics and the dimension of the PT was studied.

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Area- and Energy-Efficient Ternary D Flip-Flop Design

  • Taeseong Kim;Sunmean Kim
    • Journal of Sensor Science and Technology
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    • v.33 no.3
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    • pp.134-138
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    • 2024
  • In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

A Study on the Optimal Design of LLC Resonant Half-bridge dc-dc Converter Using a Steady-state Model with Internal Loss Resistors (내부 손실 저항이 있는 정상상태 모델을 이용한 LLC 공진형 하프 브리지 dc-dc컨버터의 최적 설계에 관한 연구)

  • Yoo, Jeong Sang;Ahn, Tae Young
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.3
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    • pp.80-86
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    • 2022
  • In this paper, the optimal design and circuit simulation verification results of an LLC resonant half-bridge dc-dc converter using a steady-state model with internal loss resistance are reported. Above all, the input/output voltage gain and frequency characteristic equations in the steady-state were derived by reflecting the internal loss resistance in the equivalent circuit. Based on the results, an LLC resonant half-bridge dc-dc converter with an input voltage of 360-420V, an output voltage of 54V, and a maximum power of 3kW was designed, and to verify the design, the PSIM circuit simulation was executed to compare and analyze the result. In particular, the operating range of the converter could be drawn from the frequency characteristic graph of the voltage gain, and when the converter was operated under light and maximum load conditions, it was confirmed that similar results were obtained by comparing simulation results and calculation results in the switching frequency characteristic graph. In addition, the change of the switching frequency with respect to the load current at each input voltage was compared with the calculated value and the simulation result. As a result, it was possible to confirm the usefulness of the analysis result reflecting the internal loss resistance proposed in this paper and the process of the optimal design.

A study for the extraction of DGS 4-port equivalent circuit and it's parameters (DGS 구조의 4-port 등가회로 및 파라미터에 대한 추출 방법에 대한 연구)

  • Son, Chang-Sin;Jeong, Myung-Sub;Choi, Wan-Seoung;Park, Jun-Seok;Lim, Jae-Bong;Choi, Hong-Goo
    • Proceedings of the KIEE Conference
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    • 2004.07c
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    • pp.2043-2045
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    • 2004
  • This thesis complemented the weak points that the existing theses did not represented a phase characteristic as the equivalent circuit by applying 4-port simulation to DGS (Defected Ground Structure) characteristic and an equivalent circuit, which are the transmission line structure that has the defect made in the ground surface. We used a distribute device and a lumped device, obtained the equivalent circuit by applying the structure of balun to a discontinuous part. An indicated DGS (Defected Ground structure) is a dumbbells-shaped single defect, we indicated satisfying a magnitude and phase characteristics by applying this equivalent circuit.

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