• Transactions on Electrical and Electronic Materials
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• v.13 no.3
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• pp.129-135
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• 2012

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.774_775
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• 2009

The shape optimization of a Thomson coil actuator used in an arc eliminator is done for fast response by adopting topology modification method. The performance of the actuator is analyzed by using an equivalent circuit method. Both shape optimization and performance analysis are accomplished based on the segmentation of plate. The effectiveness of the proposed method is proved by the comparison of results before and after the shape optimization.

• Journal of the Korea Society of Computer and Information
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• v.21 no.2
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• pp.97-103
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• 2016

This paper deals with the cycle time minimization problem that determines the productivity in printed circuit board (PCB) with n components using the m placement machines. This is known as production cycle time determination problem (PCTDP). The polynomial time algorithm to be obtain the optimal solution has been unknown yet, therefore this hard problem classified by NP-complete. This paper gets the initial assignment result with the machine has minimum unit placement time per each component firstly. Then, the balancing process with reallocation from overhead machine to underhead machine. Finally, we perform the swap optimization and get the optimal solution of cycle time $T^*$ within O(mn) computational complexity. For experimental data, the proposed algorithm can be obtain the same result as integer programming+branch-and-bound (IP+B&B) and B&B.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Journal of the Korean Society of Safety
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• v.37 no.1
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• pp.12-19
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• 2022

Circuit breakers are a crucial factor in ensuring the safety of a Direct Current (DC) grid. One type of DC circuit breaker, the Z-source DC circuit breaker (ZCB), uses a thyristor, which is a type of semiconductor switch. In the event of a fault in the circuit, the ZCB isolates the fault by generating a zero crossing current in the thyristor. The thyristor quickly and actively isolates the fault while generating a zero crossing current, but thyristor switch cannot control turn-off and the allowable current is lower than the current of the mechanical switch. Therefore, it is best to use a mechanical switch with a high allowable current capacity that is capable of on/off control. Due to the slow reaction time of mechanical switches, they may not isolate the fault during the zero crossing current time interval created by the existing circuit. In this case, the zero crossing current time can be increased by using the property that hinders the rapid change in the current of the inductor. This paper will explore whether adding system inductance to increase the zero crossing current time interval is a solution to this problem. The simulation of changing inductor and capacitor (LC) of the circuit is repeated to find an optimal change in the zero crossing current time according to the LC change and provides an inductor and capacitor range optimized for a specific load. The inductor and capacitor range are expected to provide optimization information in the form LC values for future applications of ZCB's using a mechanical switch.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1056-1067
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• 1987

This paper presents a design procedure for building block integrated circuits that is based on the digraph relaxation model. A set of optimization procedure is prosented for a minimum area and routing-fecsible placement of IC building blocks. Chip area optimization is subject to perimeter and area constraints on the component rectangles in the dissection.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.301-302
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• 2009

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• 전기의세계
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• v.24 no.5
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• pp.72-80
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• 1975

In this paper an application of the Monte Carlo method to optimum circuit design is discussed. T. Tsuda and T. Kiyono's algorithm based on the Monte Carlo method for solving multiple simul-taneous nonlinear equations is generalized to apply it to finding solutions of the constrained nonlinear optimization problem. The generalized algorithm derived here is directly applied to economical circuit design. In the cirsuit design, the object function is a cost function which is related to the cost of each circuit component. The constraint is the variance of the total system expressed by the variances of each circuit component. The design is to be determined so that the circuit has specified drift reliability with minimum cost. A practical example of economical circuit design and a general nonlinear function minimization is presented with food results.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.123-126
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• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.