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http://dx.doi.org/10.4313/TEEM.2012.13.3.129

Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing  

Hong, Sang-Jeen (Department of Electronic Engineering, Myongji University)
Kim, Hee-Yeon (Department of Electronic Engineering, Myongji University)
Han, Seung-Soo (Department of Information and Communication Engineering, Myongji University)
Publication Information
Transactions on Electrical and Electronic Materials / v.13, no.3, 2012 , pp. 129-135 More about this Journal
Abstract
A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.
Keywords
Process optimization; Tombstone; Land design; Taguchi analysis; FPC;
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