• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.156-161
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• 1996

Accurate equivalent circuit modeling using multi-circuit optimization has been perfomred for detemining small-signal model of AlGaAs/GaAs HBTs. Three equivalent circuits for a cutoff biasing and two active biasing at different curretns are optimized simultaneously to fit gheir S parameters under the physics-based constrain that current-dependent elements for one of active circuits are connected to those for another circit multiplied by the ratio of two currents. The cutoff mode circuit and the physical constrain give the advantage of extracting physically acceptable parameters, because the number of unknown variables. After this optimization, three ses of optimized model S-parameters agree well with their measured S-parameters from 0.045 GHz to 26.5GHz.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1242-1244
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• 1999

AVR parameter tuning for voltage control of power system generators has generally been done with the open-circuit model of the synchronous generator. When the generator is connected on-line and operating at rated load conditions, the AVR operates in an entirely different environment from the open-circuit conditions. This paper describes a new method for AVR parameter tuning using optimization technique with on-line linearized system model. As this method considers not only the on-line models but also the off-line open-circuit models, AVR parameters tuned by this method can give the sufficiently stable performance at the open-circuit commissioning phase and give the desired performance at the operating conditions. Also this method estimates the optimum parameters for desired performance indices that are chosen for satisfying requirements in some practical applications, the performance of the AVR can satisfy the various requirements.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.40-43
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• 1996

To design high quality products at low cost is one of very important task for engineers Design optimization for performances can be one solution in this task. This is robust design which has been proved effectively in many field of engineering design. In this paper, the concept of robust design is introduced and combined to fuzzy optimization and nonsingleton fuzzy logic system. The optimum parameter set points were obtained by the fuzzy optimization method and nonsingleton fuzzy logic system. These methods are applied to a filter circuit, a part of the audio circuit of mobile radio transceiver. The results are compared each other.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.5 no.1
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• pp.60-69
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• 1980

The computerized analysis of complicated circuits requires large memory capacity and considerable length of time. In order to enhance the efficiency of memory capacity and the executing time, Sparse Matrix is applied to the solution of simultaneous equations required for the analysis of amplification circuit. The optimization Subroutine, FMFP is utilized for the decision of optimum element parameters of an equalizer amplifier.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.58-65
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• 1993

In this research, we developed a new algorithm for hierarchical placement of integrated circuits. For efficient placement of a large circuit, the given circuit is recursively partitioned to form a hierarchy tree and then simulated-annealing-based placement method is applied at each level of the hierarchy to find a near optimum solution. During the placemtnt, global optimization is performed at high levels of the hierarchy and local optimization is performed at low levels. When compared with conventional placement methods, the new hierarchical placement method produced favorable results.

• International Journal of Control, Automation, and Systems
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• v.5 no.2
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• pp.192-199
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• 2007

This paper proposes a new printed circuit board (PCB) assembly planning method for multi-head surface mounters. We present an integer programming formulation for the optimization problem, and propose a heuristic method to solve the large NP-complete problem within a reasonable time. A dynamic programming technique is then applied to the feeder arrangement optimization and placement sequence optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.102-106
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• 2009

This paper presents the design and optimization of output matching network according to envelope for class F power amplifier(PA) which is to apply to envelope elimination and restoration(EER) transmitter. In this paper, to increase the PAE of class F power amplifier which applies to EER transmitter, the varactor diode has been used on output matching network. As envelope changes, it optimizes constitution of harmonic trap that is short circuit in 2nd-harmonic and is open circuit in 3rd-harmonic. When drain voltage changes from 25 V to 30 V, some percentage is improved in the PAE.put the abstract of paper here.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1133-1136
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• 1998

The optimization theory in this paper was down a power consumption and a chip area that this paper use a low number of transistor and compare two circuits of the input-output control. the first, design a circuit of pipeline Multiplexor in sequence of invert. the second, operated a control of N numbers of MUX using a decoder. compare a number of transistor, a chip area in semiconductor and a power consumption of two circuit.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.4
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• pp.14-21
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• 2012

This paper study a method of modeling and simulation of LED driver circuit for a design optimization. Simplified LED modeling is introduced and a driver IC, HV9910, is modeled by implementing the major function blocks. Circuit of buck type converter is constructed for simulation. Simulation includes not only the internal function of IC but also the various performance results such as LED array current control and dimming. Experiment results are also shown to prove the verification of its usage. This results show that the simulation approach is valid for a circuit optimization and a reduction of development time.