• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.12
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• pp.702-708
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• 2020

Recently, as LED display systems have become larger, research on effective power control methods for the systems has been in progress. This paper proposes a power control method to minimize power loss due to the difference in LED characteristics for each channel of a backlight unit (BLU) system. The proposed LED driver IC has a power optimization function and detects the minimum headroom voltage for constant current operation of all channels and linearly controls the DC-DC converter output. Thus, it minimizes power consumption due to unnecessary additional voltage. In addition, it does not require a voltage sensing comparator or a voltage generation circuit for each channel. This has a great advantage in reducing the chip size and for stabilization when implementing an integrated circuit. In order to verify the proposed function, an IC was designed using Cadence and Synopsys' design tools, and it was fabricated with a Magnachip 0.35um 5V/40V CMOS process. The experiments confirmed that the proposed power control method controls the minimum required voltage of the BLU system.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.3
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• pp.347-353
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• 2012

Recently, multi-functionalization (as in smart phones) has been in demand, and the connectors connecting the electrical signals of each board in a cellular phone have become key components. The miniaturization of these connectors is required to achieve a finer pitch design and enhance the electrical signal transfer capacity. However, the miniaturization of connectors reduces the structural safety, and a finer pitch design may cause contact problems under external impact. In this paper, a preliminary design for miniaturized, finer-pitch connectors is suggested for a product with 50 pins and a thickness of 0.2 mm. The assembly process of the FPCB (Flexible Printed Circuit Board) and connector was simulated to ensure the holding force between the two components and avoid overstressing. The design optimization process was performed with the Taguchi method. Fatigue analysis was also conducted to predict the fatigue life of the terminal, and the theoretical and experimental results were compared.

• Journal of the Korea Computer Industry Society
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• v.2 no.3
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• pp.369-376
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• 2001

The optimization of resonator and laser power supply has been considered to be significant for improving the efficiency of a pulsed Nd:YAG laser system. We have proposed a new method of 3-mesh parallel sequential charge and discharge circuit as a laser power supply; more compact than conventional power supply, competitive in price, easy to control the laser power density according to various material processing, and equipped with the optimum reflectivity of output coupler. In this study, we could find that the maximum laser output was obtained by using 85% of reflectivity in the case of 50[W]-class. In addition using the power supply of new method, it's possible to charge each capacitor bank with a higher energy within the given charging time adopted a new method mentioned above; namely, we can allow each capacitor to have much more charging time and storage energy. So, higher laser output was obtained than conventional power supply.

• Composites Research
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• v.24 no.1
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• pp.37-44
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• 2011

In this paper, Particle Swarm Optimization(PSO) is applied to the design of the Frequency Selective Surface(FSS) and residual stresses of hybrid radome is predicted. An equivalent circuit model with Square Loops arrays was derived and then PSO was applied for acquiring the optimized geometrical parameters with proper resonant frequency. Residual stresses occur in the FSS embedded composite structures after cocuring and have a great influence on the strength of the FSS embedded composite structures. They also effect transmission quality because of delamination. Therefore, the thermal residual stresses of FSS embedded composite structures were analyzed using finite element analysis with considering the effects of FSS pattern, and composite stacking sequence.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.2
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• pp.70-77
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• 2003

In this paper, analysis and measurement on coaxial connecter designed for packaging of microwave and micro strip transition structure are carried out. Even though researches on optimization of various kinds of transition structures have been conducted actively; however, the range of the application was very limited since they have been focused mainly on improvement of specific transmission line. Therefore, in this paper, we tried to analyze three kinds of substrates of which dielectric constants are 2,5,10 and are commercially used nowadays. Besides, we have confirmed reliability of FEM analysis, extracted equivalent circuit of transition area, found out factors determining extracted physical values, and made proof of electromagnetic variations for optimum characteristics. In addition, transition structure showing optimized characteristics on the basis of dielectric and microstrip structure was proposed. We reckon that the result of this research will apply with effect to transition design in microwave packaging development.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.935-943
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• 2015

Permanent magnetic actuators (P.M.A.s) are widely used to drive medium-voltage-class vacuum circuit breakers (V.C.B.s). In this paper, a method for design optimization of a P.M.A. for V.C.B.s is discussed. An optimal design process employing the response surface method (R.S.M.) is proposed. In order to calculate electromagnetic and mechanical dynamic characteristics, an initial P.M.A. model is subjected to numerical analysis using finite element analysis (F.E.A.), which is validated by comparing the calculated dynamic characteristics of the initial P.M.A. model with no-load test results. Using tables of mixed orthogonal arrays and the R.S.M., the initial P.M.A. model is optimized to minimize the weight of the permanent magnet (P.M.) and to improve the dynamic characteristics. Finally, the dynamic characteristics of the optimally designed P.M.A. are compared to those of the initially designed P.M.A.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1297-1300
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• 2008

A conventional linear accelerator system requires a flat-topped pulse with less than ${\pm}$ 0.5% ripple to meet the beam energy spread requirements and to improve pulse efficiency of RF systems. A pulse transformer is one of main determinants on the output pulse voltage shape. The pulse transformer was investigated and analyzed with the pulse response characteristics using a simplified equivalent circuit model. The damping factor ${\sigma}$ must be >0.86 to limit the overshoot to less than 0.5% during the flat-top phase. The low leakage inductance and distributed capacitance are often limiting factors to obtain a fast rise time. These parameters are largely controlled by the physical geometry and winding configuration of the transformer. A rise time can be improved by reducing the number of turns, but it produces larger pulse droop and requires a larger core size. By tradeoffs among these parameters, the high-voltage pulse transformer with a pulse width of 10 ${\mu}s$, a rise time of 0.84 ${\mu}s$, and a pulse droop of 2.9% has been designed and fabricated to drive a klystron which has an output voltage of 284 kV, 30-MW peak and 60-kW average RF output power. This paper describes design optimization of a high-voltage pulse transformer for high-power pulsed applications. The experimental results were analyzed and compared with the design. The design and optimal tuning parameter of the system was identified using the model simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.2
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• pp.158-163
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• 2023

Recently, the global demands for high voltage power semiconductors are increasing across various industrial fields. The use of electric cars with high safety and convenience is becoming practical, and IGBT modules of 3.3 kV and 1.2 kA or higher are used for electric locomotives. Delicate design and advanced process technology are required, and research on the optimization of high-voltage IGBT parts is urgently needed in the industry. In this study, we attempted to design a simulation process through TCAD (technology computer-aid design) software to optimize the process conditions of the fielding process among the core unit processes for an especial high yield voltage. As well, the prior circuit technology design and a ring pattern with a large number of ring formation structures outside the wafer similar to the chip structure of other companies were constructed for 3.3 kV NPT-IGBT through a unit process demonstration experiment. The ring pattern was designed with 21 rings and the width of the ring was 6.6 ㎛. By changing the spacing between patterns from 17.4 ㎛ to 35.4 ㎛, it was possible to optimize the spacing from 19.2 ㎛ to 18.4 ㎛.