• 전자공학회논문지A
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• 제33A권7호
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• pp.156-161
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• 1996

Accurate equivalent circuit modeling using multi-circuit optimization has been perfomred for detemining small-signal model of AlGaAs/GaAs HBTs. Three equivalent circuits for a cutoff biasing and two active biasing at different curretns are optimized simultaneously to fit gheir S parameters under the physics-based constrain that current-dependent elements for one of active circuits are connected to those for another circit multiplied by the ratio of two currents. The cutoff mode circuit and the physical constrain give the advantage of extracting physically acceptable parameters, because the number of unknown variables. After this optimization, three ses of optimized model S-parameters agree well with their measured S-parameters from 0.045 GHz to 26.5GHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 C
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• pp.1242-1244
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• 1999

AVR parameter tuning for voltage control of power system generators has generally been done with the open-circuit model of the synchronous generator. When the generator is connected on-line and operating at rated load conditions, the AVR operates in an entirely different environment from the open-circuit conditions. This paper describes a new method for AVR parameter tuning using optimization technique with on-line linearized system model. As this method considers not only the on-line models but also the off-line open-circuit models, AVR parameters tuned by this method can give the sufficiently stable performance at the open-circuit commissioning phase and give the desired performance at the operating conditions. Also this method estimates the optimum parameters for desired performance indices that are chosen for satisfying requirements in some practical applications, the performance of the AVR can satisfy the various requirements.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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• pp.40-43
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• 1996

To design high quality products at low cost is one of very important task for engineers Design optimization for performances can be one solution in this task. This is robust design which has been proved effectively in many field of engineering design. In this paper, the concept of robust design is introduced and combined to fuzzy optimization and nonsingleton fuzzy logic system. The optimum parameter set points were obtained by the fuzzy optimization method and nonsingleton fuzzy logic system. These methods are applied to a filter circuit, a part of the audio circuit of mobile radio transceiver. The results are compared each other.

• 한국통신학회논문지
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• 제5권1호
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• pp.60-69
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• 1980

크고 複雜한 線形回路方程式을 갖는 큰 계통의 回路를 解析하기 위해서는 매우 많은 記憶容量과 時間이 必要하다. 이러한 記憶容量과 계산 時間을 줄이기 위해서 본 論文에서는 Sparse 行列을 利用하여 增幅回路의 最適 設計를 하였다.

• 전자공학회논문지A
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• 제30A권6호
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• pp.58-65
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• 1993

In this research, we developed a new algorithm for hierarchical placement of integrated circuits. For efficient placement of a large circuit, the given circuit is recursively partitioned to form a hierarchy tree and then simulated-annealing-based placement method is applied at each level of the hierarchy to find a near optimum solution. During the placemtnt, global optimization is performed at high levels of the hierarchy and local optimization is performed at low levels. When compared with conventional placement methods, the new hierarchical placement method produced favorable results.

• International Journal of Control, Automation, and Systems
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• 제5권2호
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• pp.192-199
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• 2007

This paper proposes a new printed circuit board (PCB) assembly planning method for multi-head surface mounters. We present an integer programming formulation for the optimization problem, and propose a heuristic method to solve the large NP-complete problem within a reasonable time. A dynamic programming technique is then applied to the feeder arrangement optimization and placement sequence optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• 대한전자공학회논문지TC
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• 제46권1호
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• pp.102-106
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• 2009

본 논문은 EER(Envelope Elimination and Restoration)에 적용된 class F 전력 증폭기의 드레인 전압의 변화에 따른 출력 정합회로의 최적화에 대하여 연구하였다. EER 구조에 적용된 class F PA의 PAE(Power Added Efficiency)를 개선하기 위해 고조파 조정 회로에 Varactor 다이오드를 사용하였다. 포락선의 변화에 따라 2차 고조파는 단락 시키고 3차 고조파는 개방 시키도록 설계되었으며 본 논문에서 제안된 고조파 조정 회로를 통해 드레인 전압이 25 V에서 30 V까지 변화할 때 수 %의 PAE 개선 효과를 얻을 수 있었다.

• 한국통신학회논문지
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• 제36권11C호
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• pp.649-654
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• 2011

본 논문에선 리드 솔로몬 복호기의 오류갯수를 판별하는 마이크로콘트롤러의 새로운 설계법을 제시한다. 본 설계법을 통해 기존보다 빠르고 훨씬 회로량이 줄어든 최적화된 오류갯수 판별기용 산술논리연산장치회로를 설계할 수 있었다. 이 리드솔로몬 복호기는 거의 모든 디지털 통신 및 가전기기의 데이터 보존기기의 보호장치로 사용되어질 수 있다. 여기서는 제곱계산회로의 최소화가 가능해 병렬처리를 통해 오류갯수 판별기의 최적화를 이룰 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1133-1136
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• 1998

본 논문에서 최적화이론이란 이 논문에서 두 개의 회로를 비교하고 트랜지스터의 개수를 적게 사용하여 전력소비를 줄일 수 있었고, 면적을 적게 축소하였다. 그리고 입출력에서 사용하는 제어는 크게 두 개로 나누었다. 첫 번째로 인버터를 사용해서 순차적으로 진행하도록 한 파이프라인의 회로를 설계하였고, 두 번째로 논리회로를 이용해서 n개의 MUX를 동시에 동작하도록 제어하였다. 두 개의 회로에서 트랜지스터의 개수와 반도체 칩의 면적 그리고 소비전력을 비교하여본다.

• 조명전기설비학회논문지
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• 제26권4호
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• pp.14-21
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• 2012

This paper study a method of modeling and simulation of LED driver circuit for a design optimization. Simplified LED modeling is introduced and a driver IC, HV9910, is modeled by implementing the major function blocks. Circuit of buck type converter is constructed for simulation. Simulation includes not only the internal function of IC but also the various performance results such as LED array current control and dimming. Experiment results are also shown to prove the verification of its usage. This results show that the simulation approach is valid for a circuit optimization and a reduction of development time.