• 전기전자학회논문지
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• 제8권1호
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• pp.136-144
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• 2004

2차원 소자 시뮬레이터를 이용한 AC 해석 결과를 토대로 ESD 보호용 소자의 AC 등가회로 모델링을 시도한다. NMOS 보호용 트랜지스터의 AC 등가회로는 다소 복잡한 형태로 모델링되며, 이를 간단히 RC 직렬회로로 모델링할 경우 주파수 영역에 따라 오차가 크게 발생할 수 있음을 설명한다. 또한 싸이리스터형 pnpn 보호용 소자의 등가회로는 간단히 RC 직렬회로로 모델링될 수 있음을 보인다. 추출한 등가회로를 이용한 회로 시뮬레이션에 근거하여, 주요 RF 회로의 하나인 LNA에 ESD 보호용 소자를 장착할 경우 보호용 소자의 기생성분이 LNA의 특성에 미치는 영향에 대해 조사해 본다. NMOS 보호용 트랜지스터를 단순히 커패시터 하나만으로 모델링할 경우 회로특성의 예측에 큰 오류가 발생할 수 있음을 설명한다. 또한 제시한 pnpn 보호용 소자를 사용할 경우 보호용 소자의 장착에 의한 LNA 회로의 특성 열화가 크게 감소될 수 있음을 확인한다.

• 마이크로전자및패키징학회지
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• 제25권4호
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• pp.59-66
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• 2018

본 논문에서는 수치해석을 사용하여 반도체용 패키지에 적용된 인쇄회로기판 (PCB(printed circuit board)) 구조를 다층 구조의 소재 특성을 모델링한 것과 단일 구조라고 가정한 모델링을 적용하여 warpage를 해석함으로써 단일 구조 PCB 모델링의 유용성을 분석하였다. 해석에는 3층과 4층 회로층을 갖는 PCB가 사용되었다. 또한 단일 구조 PCB의 재료 특성값을 얻기 위해 실제 제품을 대상으로 측정을 수행하였다. 해석 결과에 의하면 PCB를 다층 구조로 모델링한 경우에 비해 단일 구조로 모델링한 경우에 warpage가 증가하여 PCB 구조의 모델링에 따른 warpage 분석결과가 분명한 유의차가 있었다. 또한, PCB의 회로층이 증가하면 PCB의 기계적 특성인 탄성계수와 관성모멘트가 증가하여 패키지의 warpage가 감소하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.171-174
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• 2005

The circuit simulation analysis and diagnosis methods are used to instruments in detail when they give apparently abnormal readings. In this paper, a new simulator through an analysis of the important circuits modeling under severe accident conditions has been designed, the realization for a body work instead of the two sorts of the Labview & Pspice as an one order command in the Labview program. The program can be shown the output graph form the circuit modeling as an order commend. The procedure for the simulator design was divided into two design steps, of which the first step was the diagnosis methods, the second step was the circuit simulator for the signal processing tool. It has three main functions which are a signal processing tool, an accident management tool, and an additional guide from the initial screen.

• Journal of Advanced Marine Engineering and Technology
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• 제36권2호
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• pp.315-320
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• 2012

일반적으로 저압 회로 보호용 장치로는 ICCB(Insulated case circuit breakers), PCB(Power circuit breakers) 그리고 MCCB(Molded case circuit breakers)를 들 수 있다. 이들 중 가장 보편적으로 사용되는 배선용 차단기(MCCB)는 휴즈 또는 개폐기의 단점인 안전성, 제어성, 협조성 등을 보완한 것이다. 차단기의 성능은 사고전류 발생 시 트립 동작이 순간적이고, 절연능력이 뛰어나야 하므로 매우 중요하다. 따라서 차단기의 개폐 성능은 매우 중요하므로 개폐 기구부의 접촉자 구조 및 접점 그리고 링크구조 등에 대한 기구학적 연구가 필요하다. 본 논문에서는 저압차단기의 기구적 동역학 모델링과 해석을 수행하여 가동자의 개리속도가 빠를수록 차단특성에 유리하다는 결론을 얻었으며, 실제 실험을 통하여 이를 검증하였다.

• 한국초전도ㆍ저온공학회논문지
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• 제5권1호
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• pp.56-59
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• 2003

As electric power systems grow to supply the increasing electric power demand short-circuit current tends to increase and impose a severe burden on circuit breakers and power system apparatuses. Thus, all electric equipment in a power system has to he designed to withstand the mechanical and thermal stresses of potential short-circuit currents. Among current limiting devices, Fault Current Limiter (FCL) is expected to reduce the short-circuit current. Especially, Superconducting Fault Current Limiters (SFCL) offer ideal performance: in normal operation the SFCL is in its superconducting state and has negligible impedance, in the event of a fault, the transition into the normal conducting state passively limits the current. The SFCL using high-temperature superconductors offers a positive resolution to controlling fault-current levels on utility distribution and transmission networks. This study contributes to the EMTDC based modeling and simulation method of DC Reactor type SFCL. Single and three phase faults in the utility system with DC reactor type SFCLs have been simulated using EMTDC in order to coordinate with other equipments, and the results are discussed in detail.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.3019-3021
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• 2005

In this paper we suggest a novel temperature detection method utilized in direct over-temperature protection circuit modeling. The suggested model detects temperature variation using Rds(on) characteristics of MOSFET, while the conventional methods are using extra devices such as a temperature sensor or an over-temperature detection transistor. The temperature-dependant MOSFET model is implemented using Spice ABM(Spice Analog Behavior Model). The direct over-temperature protection circuit was designed including it. We verified effectiveness of the temperature dependant Rds(on) model characteristics and performance of the direct over-temperature protection circuit on PSpice simulation

• 전자공학회논문지A
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• 제33A권7호
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• pp.156-161
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• 1996

Accurate equivalent circuit modeling using multi-circuit optimization has been perfomred for detemining small-signal model of AlGaAs/GaAs HBTs. Three equivalent circuits for a cutoff biasing and two active biasing at different curretns are optimized simultaneously to fit gheir S parameters under the physics-based constrain that current-dependent elements for one of active circuits are connected to those for another circit multiplied by the ratio of two currents. The cutoff mode circuit and the physical constrain give the advantage of extracting physically acceptable parameters, because the number of unknown variables. After this optimization, three ses of optimized model S-parameters agree well with their measured S-parameters from 0.045 GHz to 26.5GHz.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.607-610
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• 2003

The characteristic prediction and analysis of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. The four different structures of 3-D inductor are fabricated by using low-temperature cofired ceramic (LTCC) process. The circuit model parameters of the each building block are optimized and extracted using the partial element equivalent circuit method and HSPICE circuit simulator. Based on the model parameters, predictive modeling is applied for the structures composed of the combination of the modeled building blocks. And the characteristics of test structures, such as self-resonant frequency, inductance and Q-factor, are analyzed. This approach can provide the characteristic conception of 3-D solenoid embedded inductors for structural variations.

• ETRI Journal
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• 제28권3호
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• pp.347-354
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• 2006

The characteristic variation of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. Four different structures of a 3-D inductor are fabricated by using a low-temperature co-fired ceramic (LTCC) process, and their s-parameters are measured between 50 MHz and 5 GHz. The circuit model parameters of each building block are optimized and extracted using the partial element equivalent circuit method and an HSPICE circuit simulator. Based on the model parameters, the characteristics of the test structures such as self-resonant frequency, inductance, and quality (Q) factor are analyzed, and predictive modeling is applied to the structures composed of a combination of the modeled building blocks. In addition, characteristic variations of the 3-D inductors with different structures using extracted building blocks are also investigated. This approach can provide a characteristic estimation of 3-D solenoid embedded inductors for structural variations.

• 전기학회논문지
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• 제65권8호
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• pp.1355-1361
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• 2016

The inter-turn fault (ITF) causes the negative sequence components in the d -q voltage equation due to an increase in the unbalance of three-phase input currents. For this reason, d -q voltage equation become complicate as the voltage equation is classified into positive and negative components. In this study, we propose a simplified d -q equivalent circuit of an interior permanent magnet synchronous motor under ITF state. First, we proposed modeling method for d -q current based on the finite element method simulation results. Then, we developed the simplified d -q equivalent circuit by applying the proposed d -q current modeling.