• 한국산학기술학회논문지
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• 제4권3호
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• pp.177-182
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• 2003

Flash memory는 device 특성상 peripheral circuit을 구성하는 transistor의 종류가 다양하고, 이에 따른 각 transistor의 동작 전압 영역이 넓다. 이에 따라 설계 초기의 전기적 특성 사양 결정을 위해서는, 실리콘상에서 소자의 scale down에 따른 전기적 특성을 선 검증하는 과정이 필수적이었으며, 이로 인해 설계 및 소자 개발의 기간을 단축하기 어려웠다. 본 연구에서는 TCAD tool을 사용하여 실리콘상에서의 제작 공정을 거치지 않고, 효과적으로 model parameter를 생성할 수 있도록 하는 방법을 제안하여 전기적 특성 사양 결정과 설계 단계의 시간 지연을 감소할 수 있도록 한다. 또한 성공적 TCAD tool적용을 위해 필요한 process/device simulator의 calibration methodology와 이를 flash 메모리 소자에 대해 적용 검증한 결과를 분석한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1760-1762
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• 2002

In this work we develop an equivalent circuit model of TCP(transformer coupled plasma) source and investigate matching characteristic. The developed circuit model includes transmission line, standard-type impedance matching network and displacement current in the plasma source. The impedance of TCP is calculated by previously developed program for various source parameters and dependance of components of matching impedance on the value of source impedance is investigated.

• Journal of electromagnetic engineering and science
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• 제2권2호
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• pp.100-104
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• 2002

A proper equivalent circuit model for coupling iris has been derived in order to compensate the length of cavity in a $TE_{011}$TEX> mode cylindrical cavity filter. A method to resolve the difference in bandwidth and feature or ripple systematically has been proposed. This method can be applied to other types of waveguide cavity filter.

• 대한전자공학회논문지
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• 제27권4호
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• pp.612-619
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• 1990

In this paper, a design method of optical FSK transmitter is described using LD-FM circuit model. In the design of optical FSK transmitter, an optimum bias current was chosen using LD-FM circuit model, and an unequalized FM transfer function was determined at this current. The equalizers that can make this transfer function uniform were designed by use of a simple passive network. For the designed optical FSK transmitter, the pulse-transient and small-signal frequency-deviation responses were simulated and discussed.

• ETRI Journal
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• 제38권2호
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.3019-3021
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• 2005

In this paper we suggest a novel temperature detection method utilized in direct over-temperature protection circuit modeling. The suggested model detects temperature variation using Rds(on) characteristics of MOSFET, while the conventional methods are using extra devices such as a temperature sensor or an over-temperature detection transistor. The temperature-dependant MOSFET model is implemented using Spice ABM(Spice Analog Behavior Model). The direct over-temperature protection circuit was designed including it. We verified effectiveness of the temperature dependant Rds(on) model characteristics and performance of the direct over-temperature protection circuit on PSpice simulation

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.2067-2070
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• 2005

This paper presents an approach to evaluate the appropriate parameters for Piezoelectric ceramic utilization by adopting Impedance Method. Butterworth Van Dyke model (BVD) is considered to use as an equivalent circuit of Piezoelectric ceramic in case of no load. The experimental results from this model will be compared with the results from a circular Piezoelectric ceramic with 4.8 cm. diameter and 3 mm. thickness. The Thickness Mode vibration measured by Impedance Analyzer model 4192A can be analyzed from 1Hz to 13MHz for calculating and analyzing parameters at resonance frequency and anti-resonance frequency. These parameters are evaluated to design the efficient circuit for Piezoelectric ceramic utilization to obtain the optimal efficiency.

• 전자공학회논문지C
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• 제35C권7호
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• pp.11-19
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• 1998

A signal line potential variation due to the delta-I noise was physically investigated in CMOS integrated circuits. An equivalent circuit for the noise analysis was presented. The signal line was modeled as segmented RC-lumped circuits with the ground noise. Then the equivalent circuit was mathematically analyzed. Therebvy a new signal line potential variation model due to the switching mosie was developed. Th emodel was verified with 0.35.mu.m CMOS deivce model parameters. The model has an excellent agreement with HSPICE simulation. Thus the proposed model can be dirctly employed in the industry to design the high-performance integrted circuit design as well as integrated circuit package design.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.28-33
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• 2013

Spin-torque oscillators (STO) is a new device that can be used as a tunable microwave source in various wireless devices. Spin-transfer torque effect in magnetic multilayered nanostructure can induce precession of magnetization when bias current and external magnetic field are properly applied, and a microwave signal is generated from that precession. We proposed a semi-empirical circuit-level model of an STO in previous work. In this paper, we present a refined STO model which gives more accuracy by considering physical phenomena in the calculation of effective field. Characteristics of the STO are expressed as functions of external magnetic field and bias current in Verilog-A HDL such that they can be simulated with circuit-level simulators such as Hspice. The simulation results are in good agreement with the experimental data.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.