• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1C
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• pp.8-13
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• 2011

In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.137-148
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• 1997

Diagnostic problem solving is a major application area of knowledge-based systems research. However, most of the current approaches, both heuristic and model-based, are designed to identify single faults, and do not generalize easily to multiple fault diagnosis without exhibiting exponential behavior in the amount of computation required. In this paper, we employ a decomposition approach based on system configuration to generate an efficient algorithm for multiple fault diagnosis. The basic idea of the algorithm is to reduce the inherent combinatorial explosion that occurs in generating multiple faults by partitioning the circuit into groups that correspond to output measurement points. Rules are multiple faults by partitioning the circuit into groups that correspond to output measurement points. rules are developed for combining candidates from individual groups, and forming consistent sets of minimal candidates.

• Journal of Power Electronics
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• v.17 no.2
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.48-55
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• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.10a
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• pp.57-78
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• 2005

The vehicle routing problem (VRP) is to determine a set of feasible vehicle routes, one for each vehicle, such that each customer is visited exactly once and the total distance travelled by the vehicles is minimized. A feasible route is defined as a simple circuit including the depot such that the total demand of the customers in the route does not exceed the vehicle capacity. While there have been significant advances recently in exact solution methodology, the VRP is not a well solved problem. We find most approaches still relying on the branch and bound method. These approaches employ various methodologies to compute a lower bound on the optimal value. We introduce a new modelling approach, termed route-splitting, for the VRP that allows us to address problems whose size is beyond the current computational range of set-partitioning models. The route-splitting model splits each vehicle route into segments, and results in more tractable subproblems. Lifting much of the burden of solving combinatorially hard subproblems, the route-splitting approach puts more weight on the LP master problem, Recent breakthroughs in solving LP problems (Nemhauser, 1994) bode well for our approach. Lower bounds are computed on five symmetric VRPs with up to 199 customers, and eight asymmetric VRPs with up to 70 customers. while it is said that the exact methods developed for asymmetric instances have in general a poor performance when applied to symmetric ones (Toth and Vigo, 2002), the route splitting approach shows a competent performance of 93.5% on average in the symmetric VRPs. For the asymmetric ones, the approach comes up with lower bounds of 97.6% on average. The route-splitting model can deal with asymmetric cost matrices and non-identical vehicles. Given the ability of the route-splitting model to address a wider range of applications and its good performance on asymmetric instances, we find the model promising and valuable for further research.

• Journal of the Korean Society of Visualization
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• v.14 no.2
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• pp.52-60
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• 2016

The Passive Auxiliary Feedwater System(PAFS) is one of the advanced safety concepts adopted in the Advanced Power Reactor Plus(APR+). To validate the operational performance of the PAFS, detailed understanding of a boiling heat transfer on horizontal tube outside is of great importance. Especially, in the mechanistic boiling heat transfer model, it is important to visualize the phenomena but there are some limitations with conventional experimental approaches. In the present study, we devised a heater based on the Flexible Printed Circuit Board (FPCB) for a more comprehensive visualization and subsequently, a digital image processing technique for the bubble motion measurement was established. Using the measurement technique, important parameters of the nucleate boiling are analyzed.

• 전기의세계
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• v.18 no.6
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• pp.33-45
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• 1969

The purpose of this paper is design the most important part of sequential control systems, that is, command-treatment part, from the signal-transformation point of view. An orderly procedure is developed by which for sequential control systems the experimental design method can be reduced to the rational design method. Important in this procedure are: 1. To make total block diagram of sequential control systems by determining input and output signals of command-treatment part. 2. To partition over-all block diagram by observing each output signal. 3. To design concretely minimum block diagram by using the operational block diagram. By applying the method for partitioning the circuit to the design, the design method for sequential control systems is organized and done rationally without the aid of experiece.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.1607-1610
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• 2001

회로분할 기법은 VLSI 칩 설계 시 핵심적인 기술로서 오랫동안 연구가 행해져 왔는데, 대부분의 회로분할 휴리스틱에서 Fiduccia-Mattheyses(FM) 알고리즘을 기본 기술로 사용하고 있다. 본 논문에서도 FM 알고리즘을 기본 분한 기술로 이용하되 선형배치 및 클러스터링 기법을 추가로 적용하여 효과적인 회로 분할 알고리즘을 제안한다. MCNC 벤치마크 회로를 이용하여 제안한 알고리즘과 FM 알고리즘을 실험적으로 비교하였다. 실험결과는 회로에 따라 적게는 14%, 많게는 57%까지 개선되는 것을 보여준다.