• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1104-1109
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• 2005

In this paper, a Ka-band harmonic mixer is designed and fabricated on the base of the multiplier theory that there is a bias point to maximize the third harmonic order($3f_{LO}$) with respect to a fundamental LO frequency($f_{LO}$), which can make the high-order mixing element($f_{RF}{\pm}3f_{LO}$) to be greater than other mixing elements, Pumping a RF frequency($f_{RF}$) and LO frequency($f_{LO}$). The harmonic mixer by the proposed design method is fabricated by using a commercial GaAs MESFET device with a plastic package and overcome these disadvantages that a conventional mixer in Ka-band suffer from a high cost, inefficient productivity and circuit complexity. The harmonic mixer have a -10 dB conversion loss at the IF Sequency($3f_{LO}-f_{RF}$=1.0GHz) by selecting a gate bias voltage for the maximum third-order LO harmonic element($3f_{LO}$=34.5 GHz) as pumping LO frequency($f_{LO}$=11.5 GHz) With respect to RF Sequency ($f_{RF}$=33.5GHz)

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.175-180
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• 2015

With progress in industrialization, facilities for generating, delivering, and receiving high levels of electric power are in great demand. The scale of electric power equipment is increasing in both size and complexity. This has contributed to the development of our modern, high-tech and information-based society. However, if the generation of electric power is suspended due to unexpected accidents at power facilities or power stations, a range of equipment the operations of which are dependent on electric power can be damaged, causing substantial socioeconomic losses in an industrial society. A great deal of time and money would be expended to repair damaged facilities at a power station, causing enormous economic loss.In order to detect the deterioration processes of power cables, and to prevent the destruction of power cables, the operation status of power cables should be monitored on a regular basis. We have installed equipment at Korea Western Power Co., Ltd., located in Taean, in order to predict and prevent the destruction of power cables. This is an entirely new installation: a set of equipment invented specifically to measure the insulation resistance of power cables. Installation of the equipment does not cause the flow of earth fault current. This ensures accurate measurement of insulation resistance values by the equipment. We have been studying this equipment in order to develop preventive technology that would show the deterioration processes of power cables.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6274-6281
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• 2015

Radio-based train control system has driving headway shortening effect by real-time train interval control using two-way radio communication between onboard and wayside systems, and reduces facility investment because it does not require any track-circuit. Automatic train protection(ATP), the most significant part of the radio-based train control system, makes sure a safe distance between preceding and following trains, based on real-time train location tracing. In this paper, we propose the overall ATP train interval control algorithm to control the safe interval between trains, and preprocessing-based speed profile calculation algorithm to improve the processing speed of the ATP. The proposed speed profile calculation algorithm calculates the permanent speed limit for track and train in advance and uses as the most restrictive speed profile. If the temporary speed limit is generated for a particular track section, it reflects the temporary speed limit to pre-calculated speed profile and improves calculation performance by updating the speed profile for the corresponding track section. To evaluate the performance of the proposed speed profile calculation algorithm, we analyze the proposed algorithm with O-notation and we can find that it is possible to improve the time complexity than the existing one. To verify the proposed ATP train interval control algorithm, we build the train interval control simulator. The experimental results show the safe train interval control is carried out in a variety of operating conditions.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.120-125
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• 2016

For the purpose of protecting personal property and lives from incidents, accidents, and threats such as terrorism, video surveillance equipment has been installed and operates in many places. Video surveillance technology has gradually developed into high-quality, high-definition equipment, and a lot of products have been launched. However, closed circuit television (CCTV) equipment for security purposes can invade a person's privacy. In this paper, we propose a way to protect personal video images using meta-data in an intelligent Internet protocol (IP) camera. We designed the system to mask personal video information from meta-data, define the method of image-information access according to user privileges, and show how to utilize the meta-data during storage and recorded data searches. The suggested system complies with guidelines for CCTV installation and operation from Korea's Ministry of the Interior. Installed on only a single server so far, due to the limitations and technical difficulties of hardware performance, it has been difficult to find a method that can be applied to personal image information using real-time protection techniques. Applying the method proposed in this paper can satisfy the guidelines, reduce server costs, and reduce system complexity.

• Korean Journal of Remote Sensing
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• v.38 no.5_2
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• pp.725-735
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• 2022

Currently, disasters occurring in Korea are characterized by unpredictability and complexity. Due to these features, property damage and human casualties are increasing. Since the initial response process of these disasters is directly related to the scale and the spread of damage, optimal decision-making is essential, and information of the site must be obtained through timely applicable sensors. However, it is difficult to make appropriate decisions because indiscriminate information is collected rather than necessary information in the currently operated Disaster and Safety Situation Office. In order to improve the current situation, this study proposed a framework that quickly collects various disaster image information, extracts information required to support decision-making, and utilizes it. To this end, a web-based display system and a smartphone application were proposed. Data were collected close to real time, and various analysis results were shared. Moreover, the capability of supporting decision-making was reviewed based on images of actual disaster sites acquired through CCTV, smartphones, and UAVs. In addition to the reviewed capability, it is expected that effective disaster management can be contributed if institutional mitigation of the acquisition and sharing of disaster-related data can be achieved together.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.