• 한국정보통신학회논문지
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• 제8권2호
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• pp.365-370
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• 2004

본 논문에서는 복잡계를 이용한 비밀통신 방법을 제시한다. 복잡계 회로는 N-Double Scroll CNN 회로를 이용하였다. 동일한 여러 개의 셀을 가진 N-Double Scroll 회로를 이용하여 복잡계의 송ㆍ수신부를 구성하고 이 복잡계 송ㆍ수신부 사이에 임베딩 동기화 기법을 이용하여 동기화를 이루고, 송신부에서 정보 신호를 복잡계 신호에 합성하여 채널을 통하여 수신부에 송신 한 후 수신부에서 정보 신호와 복잡계 신호를 분리하는 기법을 제시하여 비밀 통신 가능성을 확인하였다.

• 한국인터넷방송통신학회논문지
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• 제16권3호
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• pp.137-144
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• 2016

본 논문에서는 새로운 멀티프로세서 디자인을 위한 상위 수준 합성 시스템의 회로 복잡도 최적화 ILP 알고리즘을 제안하였다. 상위수준 합성에서 가장 중요한 연산자의 특성과 데이터패스의 구조를 분석하고, 멀티사이클 연산의 스케줄링 시 가상연산자 개념을 도입함으로써, 멀티사이클 연산을 구현하는 연산자의 유형에 관계없이 공통으로 적용시킬 수 있는 ILP 알고리즘을 이용하여 증명하였다. 기술된 알고리즘의 스케줄링 성능을 평가하기 위하여, 표준벤치마크 모델인 5차 디지털 웨이브필터에 대한 스케줄링을 행한 결과, 기존의 데이터패스 스케줄링 결과와 정확하게 일치함으로서, 제시된 모든 ILP 수식이 정확하게 기술되었음을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.319-325
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• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• 전자공학회논문지A
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• 제30A권1호
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• 전자공학회논문지SC
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• 제40권3호
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• pp.145-151
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• 2003

본 논문에서는 고속의 연산동작과 낮은 회로 복잡도를 갖는 새로운 GF(2/sup m/)상의 승산기를 제안한다. 유한체 연산은 다항식 승산과 기약다항식을 적용한 모듈러 연산에 의해 전개되며, 본 논문에서는 이 두 과정을 분리하여 다루었다. 다항식 승산연산은 Permestzi의 기법을 토대로 전개하였고 기약다항식은 AOP로 하였다. 멀티플렉서를 사용하여 GF(2/sup m/)상의 승산회로를 구성하였고, 회로 복잡도와 지연시간을 타 논문과 비교하였다. 제안된 승산기는 낮은 회로 복잡도와 지연시간을 보이며, 회로의 구성이 정규성을 가지므로 VLSI 구현에 적합하다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.437-444
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• 2015

In simulation-based circuit optimization, many simulation runs may be wasted while evaluating infeasible designs, i.e. the designs that do not meet the constraints. To avoid such a waste, this paper investigates the use of support vector machine (SVM) classifiers in predicting the design's feasibility prior to simulation and the optimal selection of the SVM parameters, namely, the Gaussian kernel shape parameter ${\gamma}$ and the misclassification penalty parameter C. These parameters affect the complexity as well as the accuracy of the model that SVM represents. For instance, the higher ${\gamma}$ is good for detailed modeling and the higher C is good for rejecting noise in the training set. However, our empirical study shows that a low ${\gamma}$ value is preferable due to the high spatial correlation among the circuit design candidates while C has negligible impacts due to the smooth and clean constraint boundaries of most circuit designs. The experimental results with an LC-tank oscillator example show that an optimal selection of these parameters can improve the prediction accuracy from 80 to 98% and model complexity by $10{\times}$.

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1604-1613
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• 2018

The paper presents the equivalent circuit of an induction machine (IM) model which includes fundamental stray load and iron losses. The corresponding equivalent resistances are introduced and modeled as variable with respect to the stator frequency and flux. Their computation does not require any tests apart from those imposed by international standards, nor does it involve IM constructional details. In addition, by the convenient positioning of these resistances within the proposed equivalent circuit, the order of the conventional IM model is preserved, thus restraining the inevitable increase of the computational complexity. In this way, a compromise is achieved between the complexity of the analyzed phenomena on the one hand and the model's practicability on the other. The proposed model has been experimentally verified using four IMs of different efficiency class and rotor cage material, all rated 1.5 kW. Besides enabling a quantitative insight into the impact of the stray load and iron losses on the operation of mains-supplied and vector-controlled IMs, the proposed model offers an opportunity to develop advanced vector control algorithms since vector control is based on the fundamental harmonic component of IM variables.

• 전자공학회논문지A
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• 제33A권10호
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• pp.195-204
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• 1996

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

• 전자공학회논문지C
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• 제35C권7호
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• pp.20-29
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• 1998

As the packing density of ICs in recent submicron IC design increases, interconnects gain importance. Because interconnects directly affect on two major components of circuit performance, power dissipation and operating speed, circuit engineers are concerned with the optimal design of interconnects and the aid tool to design them. When circuit models of interconnects are given (including geometry and material information), the analysis process for the given structure is not an easy task, but conversely, it is much more difficult to design an interconnect structure with given circuit characteristics. This paper focuses on the latter process that has not been foucsed on much till now due to the complexity of the problem, and prsents a design aid tool(DATOIS) to synthesize interconnects. this tool stroes the circuit performance parameters for normalized interconnect geometries, and has two oeprational modes:analysis mode and synthesis mode. In the analysis mode, circuit performance parameters are obtained by searching the internal database for a given geometry and interpolates results if necessary . In thesynthesis mode, when a given circuit performance parameter satisfies a set of geometry condition in the database, those geometry structures are printed out.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.