• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.12
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• pp.453-460
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• 2022

As high-performance quantum computers are expected to be developed, studies are being actively conducted to build a post-quantum security system that is safe from potential quantum computer attacks. When the Grover's algorithm, a representative quantum algorithm, is used to search for a secret key in a symmetric key cryptography, there may be a safety problem in that the security strength of the cipher is reduced to the square root. NIST presents the post-quantum security strength estimated based on the cost of the Grover's algorithm required for an attack of the cryptographic algorithm as a post-quantum security requirement for symmetric key cryptography. The estimated cost of Grover's algorithm for the attack of symmetric key cryptography is determined by the quantum circuit complexity of the corresponding encryption algorithm. In this paper, the quantum circuit of the SCHWAEMM algorithm, AEAD family of SPARKLE, which was a finalist in NIST's lightweight cryptography competition, is efficiently implemented, and the quantum cost to apply the Grover's algorithm is analyzed. At this time, the cost according to the CDKM ripple-carry adder and the unbounded Fan-Out adder is compared together. Finally, we evaluate the post-quantum security strength of the lightweight cryptography SPARKLE SCHWAEMM algorithm based on the analyzed cost and NIST's post-quantum security requirements. A quantum programming tool, ProjectQ, is used to implement the quantum circuit and analyze its cost.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.105-111
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• 2024

This paper deals with the minimum linear arrangement(MinLA) of a lattice graph, to which an approximate algorithm of linear complexity O(n) remains as a viable solution, deriving the optimal MinLA of 31,680 for 33×33 lattice. This paper proposes a partitioning arrangement algorithm of complexity O(1) that delivers exact solution to the minimum linear arrangement. The proposed partitioning arrangement algorithm could be seen as loading boxes into a container. It firstly partitions m rows into r₁,r₂,r₃ and n columns into c₁,c₂,c₃, only to obtain 7 containers. Containers are partitioning with a rule. It finally assigns numbers to vertices in each of the partitioned boxes location-wise so as to obtain the MinLA. Given m,n≥11, the size of boxes C₂,C₄,C₆ is increased by 2 until an increase in the MinLA is detected. This process repeats itself 4 times at maximum given m,n≤100. When tested to lattice in the range of 2≤n≤100, the proposed algorithm has proved its universal applicability to lattices of both m=n and m≠n. It has also obtained optimal results for 33×33 and 100×100 lattices superior to those obtained by existing algorithms. The minimum linear arrangement algorithm proposed in this paper, with its simplicity and outstanding performance, could therefore be also applied to the field of Very Large Scale Integration circuit where m,n are infinitely large.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1375-1382
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• 2008

Frequency adjustable D-CRLH(dual-composite right/left handed) transmission lines, which solve the problem of design complexity and uncontrolled frequency of the existing structures, are proposed in this paper. The first design(type I), consisting of defected ground structure(DGS), island pattern in DGS, fixed stub and varactor diodes, controls $C_L$ in the parallel resonant circuit, while the second structure(type 2) composed of fixed DGS, shunt stub and diode adjusts $C_R$ in the series resonant circuit. The dual band frequency points which correspond to the meaningful electrical length of +/-90 degree in the RH/LH region are adjustable according to the bias voltage. The measurement shows that the LH frequency point which has -90 degree of electrical length are adjusted over $4.22{\sim}5.39\;GHz$ and $4.21{\sim}5.05\;GHz$ for type 1 and type 2, respectively, under $1{\sim}12\;V$ of bias voltage. In addition, the frequency Woo where RH turns over LH is controled over $3.26{\sim}4.22\;GHz$ for type 2 with the same bias condition.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1749-1753
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• 2003

We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.23-32
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• 2005

The automatic generation of circuit diagrams has been practically used in the HDL based design for decades. Nevertheless, the diagrams became too complicated for the designers to identify the signal flows in the RTL and system level designs. In this paper, we propose four techniques to enhance the roadability of the complicated diagrams. They include i) the transformation of repetitive instances and terminals into vector forms, ii) an improved loop breaking algorithm, iii) a flat tap which simplifies the two level bus ripping structure that is required for the connection of a bundle net to multiple buses, and iv) the identification of block strings, and alignment of the corresponding blocks. Towards validating the proposed techniques, the diagrams of an industrial strength design m generated. The complexity of the diagrams has been reduced by up to $90\%$ in terms of the number of wires, the aggregate wire length, and the area.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.74-82
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• 2015

As the complexity of an electronic device and the reduction of its operating voltage is progressing, susceptibility test of the chip and module for internal or external noises is essential. Although the immunity compliance of the chip was served with IEC 62132-4 Direct Power Injection method as an industry standard, in fact, EM immunity of the chip is influenced by their Power Domain Network (PDN). This paper evaluates the EM noise tolerance of a PLL and compares their noise transfer characteristics to the PLL on various PCB boards. To make differences of the PDNs of PCBs, various PCBs with or without LDO and with several types of capacitors are tested. For evaluation of discrepancies between EM characteristics of an IC only and the IC on real boards, the analysis of the noise transfer characteristics according to the PDNs shows that it gives important information for the design having robust EM characteristics. DPI measurement results show that greatly improved immunity of the PLL in the low-frequency region according to using the LDO and a frequency change of the PLL according to the DPI could also check with TEM cell measurement spectrum.