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A Study on Automatic Interface Generation by Protocol Mapping  

Lee Ser-Hoon (서강대학교 전자공학과 CAD & ES 연구실)
Kang Kyung-Goo (서강대학교 전자공학과 CAD & ES 연구실)
Hwang Sun-Young (서강대학교 전자공학과 CAD & ES 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.31, no.8A, 2006 , pp. 820-829 More about this Journal
Abstract
IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.
Keywords
SoC; Interface generation; FSM; Protocol mapping;
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