• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.65-69
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• 2010

In this study, we investigated the effects of UBM(Under Bump Metallization) and solder composition on the drop impact reliability of wafer level packaging. Fan-in type WLP chips were prepared with different solder ball composition (Sn3.0Ag0.5Cu, and Sn1.0Ag0.5Cu) and UBM (Cu 10 ${\mu}m$, Cu 5 ${\mu}m$\Ni 3 ${\mu}m$). Drop test was performed up to 200 cycles with 1500G acceleration according to JESD22-B111. Cu\Ni UBM showed better drop performance than Cu UBM, which could be attributed to suppression of IMC formation by Ni diffusion barrier. SAC105 was slightly better than SAC305 in terms of MTTF. Drop failure occurred at board side for Cu UBM and chip side for Cu\Ni UBM, independent of solder composition. Corner and center chip position on the board were found to have the shortest drop lifetime due to stress waves generated from impact.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• The Journal of the Acoustical Society of Korea
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• v.14 no.1E
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• pp.83-87
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• 1995

The implementation of the voice dodec is imjplemented by using TMS320C30, which is the floating point DSP chip from Texas Instrument. QCELP (Qualcomm Code Excited Linear Prediction) is used to encode and decode the voice. The QCELP code is implemented by the TMS320C30 C-dode. The DSP board is controlled by the PC. The PC program tranfors the voice file from and to the DSP board, which is also implemented by C-code. The voice is encoded by the DSP board and the encoded data is transferred to PC to be stored as a file. To hear the voice. the voice data file is sent to DSP board and decoded to synthesize audible voice. Two flags are used by both programs to notify the status of the operation. By checking the flags, DSP and PC decides when the voice data is transferred between them.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.408-416
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• 2010

A dumbbell-type CPW transmission-line structure has been proposed to improve the return loss of the transmission line between a driver IC and flip-chip-bonding VCSEL(Vertical Cavity Surface Emitting Laser) in a hybrid opto-electric circuit board(OECB). The proposed structure used a pair of dummy ground solder balls on the ground lines for flip-chip bonding of the VCSEL and designed the dumbbell-type CPW transmission line to improve reflection characteristics. The simulated results revealed that the return loss of the dumbbell-type CPW transmission line was 13-dB lower than the conventional CPW transmission line. A 4-dB improvement in the return loss was obtained using the dummy ground solder balls on the ground lines. The variation rate of the reflection characteristic with the variation of terminal impedances of the transmission line (at the output terminal of the driver IC and the input terminal of the VCSEL) is about ${\pm}2.5\;dB$.

• The Journal of the Acoustical Society of Korea
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• v.25 no.2
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• pp.61-71
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• 2006

An MP3 encoder chip has been designed and fabricated with the hardware and software co-design concepts. In the aspect of the software. the calculation cycles of the distortion control loop. which requires most of the calculation cycles in MP3 encoding procedure. have been reduced to $67\%$ of the original algorithm through the 'scale factor Pre-calculation'. By using a floating Point 32 bit DSP core and designing the FFT block with the hardware. we can get the additional reduction of the calculation cycles in addition to the software optimization. The designed chip has been verified using HW emulation and fabricated via 0.25um CMOS technology The fabricated chip has the size of $6.2{\time}6.2mm^2$ and operates normally on the test board in the qualitative and quantitative aspect.

• Journal of the Korea Safety Management & Science
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• v.20 no.3
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• pp.21-26
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• 2018

This paper describes result of a study on safety against a fire of charging cable for mobile phone for vehicle. Combustion on the USB cable in the car was happened while driving. Gas coming from the burning USB cable could be a reason which can make a secondary car accident since the driver also can be embarrassed while driving. In order to prevent a secondary car accident connected on the road, to research a reason why USB cable can emit gas and be burned in charging. We did simulation test with abnormal fault condition for the electronic component on the board in the USB cable. So we get the result from abnormal fault condition simulation test, for instance, shorted test for output terminal of 8 pin switch, shorted test for chip resistor after thermal aging in the condition $25^{\circ}C$, 93 % RH during 48 hours. To analysis the result of all test, Combustion on the USB cable was not the 8 pin but other electrical component such as a chip resistor. Therefore we guess that the reason for USB cable combustion in charging in a car was not 8 pin and a LED but another defective component.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.664-670
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• 2018

In modern society, CCTV, which is the eye of surveillance, is being used to collect image data in various ways in daily life. CCTV is used not only for security, surveillance, and crime prevention but also in many fields such as automobile and black box. In this paper, we have developed a STM32F407 ARM chip based camera system for various applications. In order to develop camera system, modeling of camera system based on 3D structure was carried out in SolidWorks environment. The PCB board design was developed to extract the PCB parts from the camera system modeling files into iges files, convert them from the Altium Designer tool into 3D and 2D boards, After designing the camera system circuit and PCB, we have been studying the implementation of the stable system by using TRM (Thermal Risk Management) tool to cope with the heat simulation generated on the board.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.54-58
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• 2012

In this paper, we implemented total monitoring system in which LED light turned on only when user detected and LED light turned out only when user disappeared. This system is composed of two modules, one is HW board based on Micro Controller and the other is SW control system based on Web server. Micro controller board is based on ATMega2560 chip which is connected with Infra Red and Ultra sonic sensors. Web based monitoring system was designed can be used in smart device. The validity of this monitoring system was proved by integration test of two modules.