• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.7-15
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• 2008

In this paper, the Chip-On-Flex (COF) assembly process using anisotropic conductive films (ACFs) was investigated and the reliability of COF assemblies using ACFs was evaluated. Thermo-mechanical properties of ACFs such as coefficient of thermal expansion (CTE), storage modulus (E'), and glass transition temperature $(T_g)$ were measured to investigate the effects of ACF material properties on the reliability of COF assemblies using ACFs. In addition, the bonding conditions for COF assemblies using ACFs such as time, temperature, and pressure were optimized. After the COF assemblies using ACFs were fabricated with optimized bonding conditions, reliability tests were then carried out. According to the reliability test results, COF assemblies using the ACF which had lower CTE and higher $T_g$ showed better thermal cycling reliability. Consequently, thermo-mechanical properties of ACFs, especially $T_g$, should be improved for high thermal cycling reliability of COF assemblies using ACFs for compact camera module (CCM) applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.122-131
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• 2003

In this study, some characteristics of conductive and non-conductive adhesive inter-connections are derived, based on data from literature and own projects. Assembly of flip chip on flex is taken as a carrier. Potential failure mechanisms of adhesive interconnections reported in literature are reviewed. Some methods that can be used to evaluate the quality of adhesive interconnections and to evaluate their aging behavior are given. Possible finite element simulation approaches are introduced and the required critical materials properties are summarized. Response to temperature and moisture, resistance to reflow soldering and resistance to rapid change in temperature and humidity are elaborated. The effect of post cure during accelerated testing is discussed. This study shows that only a combined approach using finite element simulations, and use of appropriate experimental evaluation methods can result in revealing, understanding and quantifying the complex degradation mechanisms of adhesive interconnections during aging.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.373-376
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• 1999

In tills paper, we design it decoder for the FLEX high speed paging protocol. The decoder that we design consists of a synchronizer, a de-interleaver, a error corrector and a packet builder In the FLEX protocol, a word is coded using HCH algorithm. In this design, we do not use a look-up table in order to decrease a chip area of the BCH decoder. The simulation result shows that the decoder is correctly designed

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.539-545
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• 2000

A 40-Mb/s, 64-state, R= 1/2, 3 bit soft decision Viterbi decoder based on Radix-4 method has been designed and fabricated using a FLEX10K CPLD chip in this paper. In order to implement the high-speed Viterbi decoder, the architectures of adder-compare-select(ACS), branch metric calculation(BMC), trace back(TB) are present. In practical designed by ASIC, the speed is faster than that of CPLD by 6~7 times. Therefore, 40 Mb/s Viterbi decoder architecture can be used for high-speed wireless multimedia communications with 200 Mb/s.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.7-8
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• 2007

Ti을 전극으로 한 RF plasma 를 사용한 표면 처리와 200 eV 이하의 저에너지 반응성 이온빔을 사용한 PI 표면 처리에 의해 초기 및 내열성이 우수한 COF 용 FCCL를 제작하였다. 임계 rf power 이상에서 새롭게 $TiO_2$층의 형성이 접착력 증대의 원인이었으며, Ni-Cr-Zn의 삼원계 접착층의 내열성 향상 특성 등을 연구하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• Restorative Dentistry and Endodontics
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• v.10 no.1
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• pp.193-198
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• 1984

This study was conducted to compare the chip removal capability of root canal enlarging instruments. Fifty five buccal or mesial canals from upper and lower molar teeth were randomly selected and divided into three groups; Reamer, K-type file and K-flex file. Fifteen canals in each group were individually enlarged with one of three tested instruments and irrigated with 5cc of normal saline solution. After instrumentation, each canal was dried with paper point and the canal was splited longitudinally and the cleanness of root canal surface was evaluated under stereoscope by three observers. The results were as follows; 1. Most of the canals experimented showed varying degree of the presence of debris. 2. The canals prepared with reamers showed the most clean canal surface. 3. There was no significant difference in debridement effect between k-type file and k-flexfile.

• Journal of Advanced Navigation Technology
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• v.1 no.1
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• pp.23-34
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• 1997

A multi-channel digital GPS receiver has been developed including a RF-to-IF engine (engine 1), a digital signal processing engine (engine 2) with a microprocessor interfacing, and a navigation software. A high speed SiGe heterojunction bipolar transistor (HBT) as a active device has been mounted on chip-on-board (COB) type hybrid ICs such as LNA, mixer, and VCO in RF front-end of the engine 1 board. A 6-channel digital correlator together with a real-time clock and a microprocessor interface has been realized using an Altera Flex 10K FPGA as well as ASIC technology. Navigation software controlling the correlator for GPS signal tracking, retrieval and storing a message retrieval, and position calculation has been implemented. The GPS receiver was tested using a single channel STR2770 simulator. Successful navigation message retrieval and position determination was confirmed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.62-71
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• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.