• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.60-67
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• 2013

Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• The Journal of Korean Medicine
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• v.24 no.2
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• pp.148-158
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• 2003

Backgrounds & Objectives: In many recent studies, molecular biological methods have been used to investigate the role of cytokines in pathogenesis and new therapeutic targets of asthma. Recently, as a method of research on the gene expression, they are applying another method which assays multiple gene expressions at the same time by the microarray. In this study, the antioxidant effect, the inhibitory effect against interleukin-4 and the effect on the CD/cytokine gene expression in PBMC (peripheral blood mononuclear cells) was evaluated by using cDNA microarray chip of Chungsangboha-tang. Methods: Experimental studies were performed for the antioxidant effect of Chungsangboha-tang on DPPH (1, 1-diphenyl-2-picrylhydrazyl) solution, for the IL-4-inhibiting effect on BALB/c mouse spleen, and for the gene expression effect on PBMC (peripheral blood mononuclear cells) with microarray. Results: Chungsangboha-tang showed antioxidant effect dose-dependently. Chungsangboha-tang inhibited interleukin-4 dose-dependently and showed significant difference in 10ug/ml and 100ug/ml of test groups. There was no 2 more times upregulated genes than in the control group by using cDNA microarray chip of Chungsangbohn-tang, but there were 140%-200% upregulated genes. There was no 2 more times downregulated genes than in the control group by using cDNA microarray chip of Chungsangboha-Tang, but there was 50%-75% downregulated genes. Conclusions: This study showed that Chungsangboha-tang has an antioxidant effect and inhibition of Interleukin-4, but further studies are necessary with microarray.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of Korea Multimedia Society
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• v.10 no.12
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• pp.1585-1590
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• 2007

This paper introduces adaptive PRML (Partial Response Maximum Likelihood) architecture with PR (a,b,c,d,e) channel type for the improved readability of high-density optical discs with capacity greater than 30GB. The proposed PRML architecture consists of an adaptive equalizer, a Viterbi detector and a channel identifier. Detailed description for each component is included. The architecture is implemented in chip and also confirmed its performance on the test board mounting the chip. Test results show that the proposed 5-tap PRML architecture is well operated, and less than $2{\times}10^{-4}$ of BER (Bit Error Rate) is achieved with radial and tangential tilt margin of ${\pm}0.6^{\circ}$ on self-made 30GB BD at 1x speed.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.4
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• pp.30-36
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• 2004

The development of LD(Laser Diode) tester and its control system based on the graphical programming language(LabVIEW) is addressed. The ill tester is used to check the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the Detector(optic fiber and photo diode) are very small, therefore the test device needs high accuracy. But each motion part of the test device could not accomplish high accuracy due to the limit of the mechanical performance. So, an image processing with machine vision is proposed to compensate for the error. By adopting our method we can reduce the error of position within $\pm$5$\mu\textrm{m}$.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.206-210
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• 2003

In this paper, we design standard cell libraries using the 0.18um deep submircom CMOS process, and port them into a P&R (Placement and Routing) CAD tool. A simple test chip has been designed in order to verify the functionalities of the 0.18um standard cell libraries whose technical process was provided by Anam semiconductor. Through these experiments, we have found that the new 0.18um CMOS process can be successfully applied to automatic digital system design.

• Publications of The Korean Astronomical Society
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• v.13 no.1 s.14
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• pp.99-109
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• 1998

Korea Astronomy Observatory (KAO) recently developed a new model of CCD imaging system for astronomical purpose. This paper presents system structure and electrical circuit descriptions with the performance of the CCD imaging system. The developed system can handle astronomical image acquisition with additional functions of on-chip binning, sub-image acquisition using a SITe $1024\times1024$ CCD chip. Particularly the controller design of the system allows us great flexibility and versatility with the software system control and it is possible to cope with any format CCDs by any manufactures, in principle. The system performances are derived by mean variance test in our laboratory, which shows that the total system noise 10.5e-(R.M.S), Gain 1.9e-/ ADD, non-linearity $0.37\%$

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.27-32
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• 2002

In this paper, global full 3D finite element analysis fatigue models are constructed for flip-chip BGA on board to predict the creep fatigue life of solder joints during the thermal cycling test. The fatigue model applied is based on Darveaux's empirical equation approach with non-linear viscoplastic analysis of solder joints. It was estimated by the creep life as the variations of the four kinds of thermal cycling test conditions, pad structure, composition and size of solder ball. The shortest fatigue life of results was obtained at the thermal cycling testing condition of -65℃ ∼ 150℃. It was increased about 3.5 times in comparison with that of 0℃ ∼ 100℃. As the change of pad structure at the same other conditions, the fatigue life of SMD structure increased about 5.7% as compared with NSMD structure. Consequently, it was confirmed that the fatigue life became short as the creep strain energy density increased in solder joint.

• ETRI Journal
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• v.29 no.3
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• pp.371-380
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• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.