Browse > Article
http://dx.doi.org/10.5573/ieek.2013.50.9.060

Reduced Pin Count Test Techniques using IEEE Std. 1149.7  

Lim, Myunghoon (Department of Computer Science & Engineering, Hanyang University)
Kim, Dooyoung (Department of Computer Science & Engineering, Hanyang University)
Mun, Changmin (Department of Computer Science & Engineering, Hanyang University)
Park, Sungju (Department of Computer Science & Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.9, 2013 , pp. 60-67 More about this Journal
Abstract
Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.
Keywords
Reduced Pin Count Test; Test Cost Reduction; IEEE Std. 1149.7; IEEE Std. 1500;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 J. Jahangiri, N. Mukherjee, C. Wu-Tung, S. Mahadevan, and R. Press, "Achieving High Test Quality with Reduced Pin Count Testing," in Proc. of IEEE Asian Test Symposium, pp. 312-317, Dec 2005.
2 이현빈, 한주희, 김병진, 박성주, "IEEE 1500 래퍼를 이용한 효과적인 AMBA 기반 시스템-온-칩코아 테스트", 대한전자공학회 논문지, 제45권 SD편 2호, pp.61-68, Feb 2008.   과학기술학회마을
3 S. Hwang and J. A. Abraham, "Test Data Compression and Test Time Reduction Using an Embedded Microprocessor," IEEE Trans. on VLSI Systems, Vol. 11, pp. 853-862, Oct 2003.   DOI   ScienceOn
4 H. Hashempour, F. J. Meyer, and F. Lombardi, "Analysis and Evaluation of Multisite Testing for VLSI," IEEE Trans. on Instrumentation and Measurement, Vol. 54, pp.1770-1778, Oct 2005.   DOI   ScienceOn
5 Adam. W. L., "Doing More with Less - An IEEE 1149.7 Embedded Tutorial : Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary-Scan Architecture," in Proc. of IEEE Test Conf., pp.1-10, Austin, US, Nov 2009.
6 H. Yi, J. Song, and S. Park "Low-Cost Scan Test for IEEE-1500-Based SoC,"" IEEE Transactions on Instrumentation and Measurement, Vol. 57, pp.1071-1078, May 2008.   DOI   ScienceOn
7 J. Song, P. Min, H. Yi, and S. Park, "Design of Test Access Mechanism for AMBA Based System-on-a-Chip," IEEE VTS, pp. 375-380, Berkeley, US, May 2007.
8 "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture," IEEE Std1149.7- 2009, pp.c1-985, Feb 2010.
9 H. Vranken, et al, "Enhanced Reduced Pin-Count Test for Full-Scan Design," in Procs. of IEEE International Test Conference, pp. 738-747, 2001.
10 Y. Zorian, A. Yessayan, "IEEE 1500 utilization in SoC design and test," IEEE proc. of International Test Conference, Nov 2005.
11 송재훈, 오정섭, 박성주, "AMBA 기반 SoC의 병렬코어 테스트를 위한 효과적인 테스트 설계 기술", 대한전자공학회 논문지, 제48권 SD편 2호, pp.44-54, Feb 2011.