• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1303-1310
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• 2016

In this paper, electrocardiogram (ECG) analog front end with supply voltage of 0.5V has been designed and verified by measurements of fabricated chip. ECG is composed of instrument amplifier, 6th order gm-C low pass filter and variable gain amplifier. The instrument amplifier is designed to have gain of 34.8dB and the 6th order gm-C low pass filter is designed to obtain the cutoff frequency of 400Hz. The operational transconductance amplifier of the low pass filter utilizes body-driven differential input stage for low voltage operation. The variable gain amplifier is designed to have gain of 6.1~26.4dB. The electrocardiogram analog front end are fabricated in TSMC $0.18{\mu}m$ CMOS process with chip size of $858{\mu}m{\times}580{\mu}m$. Measurements of the fabricated chip is done not to saturate the gain of ECG by changing the external resistor and measured gain of 28.7dB and cutoff frequency of 0.5 - 630Hz are obtained using the supply voltage of 0.5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.310-310
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• 2012

최근 전자산업의 발달에 따른 전자제품의 소형화 및 고기능화 요구에 대응하기 위하여 저항(resistor), 커패시터(capacitor), IC (integrated circuit) 등의 수동소자를 개별 칩(discrete chip) 형태로 형성하여 기판의 표면에 실장하는 기술이 일반화되고 있다. 그러나, 수동 소자의 내장 기술은 기판의 패턴 밀도의 급격한 향상과 더불어 수동소자의 내장 공간도 협소해지는 문제점이 있다. 상기의 문제점을 해결하기 위해 개별 칩 형태의 내장형 저항체를 박막 형태의 내장 저항체를 구현하는 기술의 개발이 최근 주목을 받고 있다. 박막 저항체는 기존의 권선저항 및 후막저항과 비교하여 정밀한 온도저항계수를 가지며 이동통신에 적용시 고주파 영역(GHz)에서의 안정성과 주파수 특성이 좋다는 장점들을 가지고 있다. 박막 저항 물질로는 높은 경도와 우수한 열적 안정성을 가지고 있는 TaN (tantalum nitride)이 주로 사용되고 있다. 일반적으로, TaN 박막은 스퍼터링을 사용하며 제조되며 TaN 박막의 성질은 탄탈륨과 질소의 화학정량비, 박막의 결함 정도, 또는 공정압력 및 증착 온도, 플라즈마 파워 등과 같은 공정조건 등의 변화에 민감하게 변화하므로, TaN 박막의 다양한 연구가 더 필요한 실정이다. 본 연구에서는 반응성 마크네트론 스퍼터링을 사용하여 TaN 박막을 Si 기판 위에 증착하였고 TaN 박막의 원하는 특성을 제어할 수 있도록 질소 분압과 total gas volume을 조절하여 공정을 최적화하는 연구를 진행하였다. 또한 tensile pull-off 방법을 이용하여 TaN 박막의 부착강도를 평가하였고, 온도 사이클 및 고온고습 환경에 노출된 TaN 박막들의 열화 특성들에 대하여 연구하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.23-30
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• 2006

This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.

• Journal of the Korea Society of Computer and Information
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• v.6 no.2
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• pp.8-13
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• 2001

We demonstrate a pulsed CO$_2$laser with long pulse duration of millisecond order in the low pressure less than 30 Torr. A new power supply for our laser system switches the voltage of AC power line(60㎐) directly. The power supply doesn't need elements such as a rectified bridge, energy-storage capacitors. and a current-limiting resistor in the discharge circuit. In order to control the laser output power, the pulse repetition rate is adjusted up to 60㎐ and the firing angle of SCR gate is varied from 30˚ to 150˚. A ZCS(Zero Crossing Switch) circuit and a PIC one-chip microprocessor are used to control the gate signal of SCR precisely. The maximum laser output is 23W at the total pressure of 18 Torr, the pulse repetition rate of 60㎐, and SCR gate firing angle of 90˚. In addition, the obtained laser pulse width is approximately 3㎳(FWHM)

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2729-2734
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• 2011

In this paper, an active replica Low-dropout(LDO) regulator with DC voltage matching circuit is presented. In order to match the voltage between replica and output of regulator, DC voltage matching circuit is designed. The active replica low dropout regulator has higher Power Supply Rejection(PSR) than that of conventional regulator. The designed DC voltage matching circuit can reduce the drawback that may be occurred in replica regulator. And using fully active element in regulator can reduce the chip area and heat noise with resistor. As results of HSPICE simulation with 0.35um CMOS parameter, the designed active replica LDO regulator achieves Power Supply Rejection, -28@10Hz better than -17@10Hz of conventional replica regulator without DC matching circuit. And the output voltage is 3V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.16-22
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• 2009

Integrated circuit of a pulse-type neuron for Hodgkin-Huxley model is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Proposed pulse-type neuron model consist of input stage with summing function and pulse generating block which make neuron pulse above threshold value. Pulse generating circuit consist of several transistors, capacitors and negative resistor with a charge supply function. SPICE simulation results show that neuron pulse is generated above threshold current of 70 nA. Measurements of the fabricated pulse type neuron chip in condition of 5 V power supply are shown and compared with the simulated results.