• Title/Summary/Keyword: Chip resistor

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A Study on the Adjusting Output Energy of the $CO_2$ Laser Controlled Directly in AC Power Line

  • Noh, Ki-Kyong;Jeong, Jong-Jin;Chung, Hyun-Ju;Kim, Hee-Je
    • KIEE International Transactions on Electrophysics and Applications
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    • v.5C no.4
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    • pp.152-154
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    • 2005
  • We demonstrate a simple $CO_2$ laser by controlling firing angle of a TRIAC switch in ac power line. The power supply for our laser system switches the voltage of the AC power line (60Hz) directly. The power supply does not need elements such as a rectifier bridge, energy-storage capacitors, or a current-limiting resistor in the discharge circuit. In order to control the laser output power, the pulse repetition rate is adjusted up to 60Hz and the firing angle of TRIAC gate is varied from $45^{circ}$ to $135^{circ}$. A ZCS(Zero Crossing Switch) circuit and a PIC one-chip microprocessor are used to control the gate signal of the TRIAC precisely. The maximum laser output of 40W is obtained at a total pressure of 18 Torr, a pulse repetition rate of 60Hz, and a TRAIC gate firing angle of $90^{circ}$.

Study on the Excessive Current Noise in $RuO_2$ Thick Film Resistors (산화루테늄계 후막 저항기의 과도한 전류잡음에 관한 고찰)

  • 김지호;김진용;임한조;신철재;박홍이
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.3
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    • pp.79-86
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    • 1992
  • The cause of excess current noise which appears some times in RuO$_2$ thick film chip resistors and the process to reduce such noise are investigated. We observed that too large thermal expansion coefficients of resistor paste and electrode metal paste can induce the mechanical stress and microcracks in the contact region of the two sintered materials. Such microcracks result in the reduction of conduction paths in the sintered electrode and this provokes the increase of the resistance value and the current noise. Such excessive current noise induced by microcracks could be reduced or even eliminated by using an enlarged overcoat patterns in the plating process or by adding an additional annealing process before plating.

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Design of Small-Area and High-Reliability 512-Bit EEPROM IP for UHF RFID Tag Chips (UHF RFID Tag Chip용 저면적·고신뢰성 512bit EEPROM IP 설계)

  • Lee, Dong-Hoon;Jin, Liyan;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.2
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    • pp.302-312
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    • 2012
  • In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

Thermal Shock Cycles Optimization of Sn-3.0 Ag-0.5 Cu/OSP Solder Joint with Bonding Strength Variation for Electronic Components (Sn-3.0 Ag-0.5 Cu/OSP 무연솔더 접합계면의 접합강도 변화에 따른 전자부품 열충격 싸이클 최적화)

  • Hong, Won-Sik;Kim, Whee-Sung;Song, Byeong-Suk;Kim, Kwang-Bae
    • Korean Journal of Materials Research
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    • v.17 no.3
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    • pp.152-159
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    • 2007
  • When the electronics are tested with thermal shock for Pb-free solder joint reliability, there are temperature conditions with use environment but number of cycles for test don't clearly exist. To obtain the long term reliability data, electronic companies have spent the cost and times. Therefore this studies show the test method and number of thermal shock cycles for evaluating the solder joint reliability of electronic components and also research bonding strength variation with formation and growth of intermetallic compounds (IMC). SMD (surface mount device) 3216 chip resistor and 44 pin QFP (quad flat package) was utilized for experiments and each components were soldered with Sn-40Pb and Sn-3.0 Ag-0.5 Cu solder on the FR-4 PCB(printed circuit board) using by reflow soldering process. To reliability evaluation, thermal shock test was conducted between $-40^{\circ}C\;and\;+125^{\circ}C$ for 2,000 cycles, 10 minute dwell time, respectively. Also we analyzed the IMCs of solder joint using by SEM and EDX. To compare with bonding strength, resistor and QFP were tested shear strength and $45^{\circ}$ lead pull strength, respectively. From these results, optimized number of cycles was proposed with variation of bonding strength under thermal shock.

Design of Single Power CMOS Beta Ray Sensor Reducing Capacitive Coupling Noise (커패시터 커플링 노이즈를 줄인 단일 전원 CMOS 베타선 센서 회로 설계)

  • Jin, HongZhou;Cha, JinSol;Hwang, ChangYoon;Lee, DongHyeon;Salman, R.M.;Park, Kyunghwan;Kim, Jongbum;Ha, PanBong;Kim, YoungHee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.4
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    • pp.338-347
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    • 2021
  • In this paper, the beta-ray sensor circuit used in the true random number generator was designed using DB HiTek's 0.18㎛ CMOS process. The CSA circuit proposed a circuit having a function of selecting a PMOS feedback resistor and an NMOS feedback resistor, and a function of selecting a feedback capacitor of 50fF and 100fF. And for the pulse shaper circuit, a CR-RC2 pulse shaper circuit using a non-inverting amplifier was used. Since the OPAMP circuit used in this paper uses single power instead of dual power, we proposed a circuit in which the resistor of the CR circuit and one node of the capacitor of the RC circuit are connected to VCOM instead of GND. And since the output signal of the pulse shaper does not increase monotonically, even if the output signal of the comparator circuit generates multiple consecutive pulses, the monostable multivibrator circuit is used to prevent signal distortion. In addition, the CSA input terminal, VIN, and the beta-ray sensor output terminal are placed on the top and bottom of the silicon chip to reduce capacitive coupling noise between PCB traces.

Implementation of AES and ARIA algorithm with Secure Structure for Power Analysis using LFSR Masking

  • Kang, Young-Jin;Kim, Ki-Hwan;Lee, Hoon Jae
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.1
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    • pp.79-86
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    • 2020
  • In this paper, we analyzed the case vulnerable to the power analysis attack of the ARIA algorithm and AES algorithm. Through this, we propose an algorithm with a safe structure for power analysis and prove through experiment. The proposed technique is a masking method using LFSR with a cyclic structure. To verify this, 1000, 2000, and 4000 power traces were collected, and the corresponding results are shown and proved. We used ATmega328 Chip for Arduino Uno for the experiment and mounted each algorithm. In order to measure the power consumption, a resistor was inserted and then proceeded. The analysis results show that the proposed structure has a safe structure for power analysis. In the future, we will study ways to lead to performance enhancement.

An 8b 200MHz Time-Interleaved Subranging ADC With a New Reference Voltage Switching Scheme (새로운 기준 전압 인가 방법을 사용하는 8b 200MHz 시간 공유 서브레인징 ADC)

  • Moon, Jung-Woong;Yang, Hee-Suk;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.4
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    • pp.25-35
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    • 2002
  • This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

An Improved Side Channel Power Analysis with OP-Amp (OP-Amp를 적용한 향상된 부채널 전력분석 방법)

  • Kim, JinBae;Ji, JaeDeok;Cho, Jong-Won;Kim, MinKu;Han, Dong-Guk
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.25 no.3
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    • pp.509-517
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    • 2015
  • Side Channel Analysis of applying the power-consumption was known as effective method to analyze the key of security device based on chip. The precedential information of power-consumption was measured by the voltage distribution method using by series connection of resistor. This method was dependent on the strength of the voltage. If the voltage cannot be acquired much information which is involved with the key, the information of power-consumption significantly might be influenced by noise. If so, some of the information of power-consumption might be lost and distorted. Then, this loss can reduce the performance of the analysis. For the first time, this paper will be introduced the better way of the improvement with using the method of Current to Voltage Converter with OP-Amp. The suggested method can reduce the effect of the noise which is included in the side channel information. Therefore we can verify the result of our experiments which is provided with the improvement of the performance of side channel analysis.

Evaluation of Bonding Properties of Epoxy Solder Joints by High Temperature Aging Test (고온 시효 시험에 따른 Epoxy 솔더 접합부의 접합 특성 평가)

  • Kang, Min-Soo;Kim, Do-Seok;Shin, Young-Eui
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.1
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    • pp.6-12
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    • 2019
  • Bonding properties of epoxy-containing solder joints were investigated by a high temperature aging test. Specimens were prepared by bonding an R3216 standard chip resistor to an OSP-finished PCB by a reflow process with two basic types of solder (SAC305 & Sn58Bi) pastes and two epoxy-solder (SAC305+epoxy & Sn58Bi+epoxy) pastes. In all epoxy solder joints, an epoxy fillet was formed in the hardened epoxy, lying around the outer edge of the solder joint, between the chip and the Cu pad. In order to analyze the bonding characteristics of solder joints at high temperatures, a high-temperature aging test at $150^{\circ}C$ was carried out for 14 days (336 h). After aging, the intermetallic compound $Cu_6Sn_5$ was found to have formed in the solder joint on the Cu pad, and the shear stress on the conventional solder joint was reduced by a significant amount. The reason that the shear force did not decrease much, even though in epoxy solder, was thatbecause epoxy hardened at the outer edge of the supported solder joints. Using epoxy solder, strong bonding behavior can be ensured due to this resistance to shear force, even in metallurgical changes such as those where intermetallic compounds form at solder joints.

A Study on Effect of Pad Design on Assembly and Adhesion Reliability of Surface Mount Technology (SMT) (표면실장기술(SMT)의 조립 및 접합 신뢰성에 대한 패드설계의 영향에 관한 연구)

  • Park, Dong-Woon;Yu, Myeong-Hyeon;Kim, Hak-sung
    • Journal of the Microelectronics and Packaging Society
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    • v.29 no.3
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    • pp.31-35
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    • 2022
  • Recently, with the 4th industrial revolution, the demand for high-density semiconductors for large-capacity data processing is increasing. Researchers are interested in researching the reliability of surface mount technology (SMT). In this study, the effect of PCB pad design on assembly and adhesion reliability of passive component was analyzed using design of experiment (DOE). The DOE method was established using the pad length, width, and distance between pads of the PCB as variables. The assembly defect rate of the passive element after the reflow process was derived according to the misplacement direction of the chip resistor. The shear force between the passive element and the PCB was measured using shear tests. In addition, the shape of the solder according to the pad design was analyzed through cross-sectional analysis.