• ETRI Journal
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• 제45권1호
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• pp.163-170
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• 2023

We report an electroabsorption modulator (EAM)-integrated distributed Bragg reflector laser diode (DBR-LD) capable of supporting a high data rate and a wide wavelength tuning. The DBR-LD contains two tuning elements, plasma and heater tunings, both of which are implemented in the DBR section, which have blue-shift and red-shift in the Bragg wavelength through a current injection, respectively. The light created from the DBR-LD is intensity-modulated through the EAM voltage, which is integrated monolithically with the DBRLD using a butt-joint coupling method. The fabricated chip shows a threshold current of approximately 8 mA, tuning range of greater than 30 nm, and static extinction ratio of higher than 20 dB while maintaining a side mode suppression ratio of greater than 40 dB under a window of 1550 nm. To evaluate its modulation properties, the chip was bonded onto a mount including a radiofrequency line and a load resistor showing clear eye openings at data rates of 25 Gb/s nonreturn-to-zero and 50 Gb/s pulse amplitude modulation 4-level, respectively.

• ETRI Journal
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• 제46권3호
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• pp.550-563
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• 2024

A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.

• 대한기계학회논문집B
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• 제30권2호
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• pp.110-116
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• 2006

A syringe pump or a device using high electric voltage has been used for controlling flows inside a LOC (lab-on-a-chip). Compared to LOC, however, these microfluidic devices are large and heavy that they are burdensome for a portable ${\mu}-TAS$ (micro total analysis system). In this study, a new flow control technique employing pressure regulators and pressure chambers was developed. This technique utilizes compressed air to control the micro-scale flow inside a LOC, instead of a mechanical actuator or an electric power supply. The pressure regulator controls the output air pressure by adjusting the variable resistor attached. We checked the feasibility of this system by measuring the flow rate inside a capillary tube of $100{\mu}m$ diameter in the Re numbers ranged from 0.5 to 50. In addition, the performance of this flow control system was compared with that of a conventional syringe pump. The developed flow control system was found to show superior performance, compared with the syringe pump. It maintains automatically the: air pressure inside a pressure chamber whether the flow inside the capillary tube is on or off. Since the flow rate is nearly proportional to the resistance, we can control flow in multiple microchannels precisely. However, the syringe pump shows large variation of flow rate when the fluid flow is blocked in the microchannel.

• 한국정보처리학회논문지
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• 제2권1호
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• pp.66-74
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• 1995

이 논문에서는 고속 저전력 분야에 적용하기 위한 8비트, 15MHz A/D 변환기 설계 에 관해 기술한다. 2단 플래시 방식인 서브레인징 구조 A/D 변환기에서 칩 면적을 줄 이기 위해 저항의 수를 감소시킨 전압분할 회로를 설계하였다. 비교기는 80 dB의 이득, 50 MHz의 대역폭, 오프셋 전압이 0.5mV이고, 전압분할 회로의 최대오차는 1mV이다. 설계된 A/D변환기는 ＋5/-5V 공급 전압에 대해 전력소비가 150mW, 지연시간이 65ns 이다. A/D 변환기는 N-well공정을 이용하여 설계하고, 제작하였다. 제안된 변환기는 고속, 저전력, 소형 단일 칩 아날로그-디지탈 혼합 시스템 응용에 적합하다. 시뮬레이 션은 PSPICE를 이용하여 수행하였고, 1차 가공된 칩을 데스트 하였다.

• 대한전자공학회논문지SD
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• 제47권3호
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• pp.18-27
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• 2010

본 논문에서는 offset self-calibration 기법을 적용한 7-bit 1GSPS folding-interpolation A/D 변환기를 제안한다. 제안하는 A/D 변환기는 folding rate 2, interpolation rate 8의 1+6 구조로 고속 동작에 적합하게 설계되었다. 또한 offset self-calibration 회로를 설계하여 공정 mismatch, 기생 저항, 기생 캐패시턴스 등에 의한 offset-voltage의 변화를 감소시켜 A/D 변환기의 성능 특성을 향상 시켰다. 제안하는 A/D 변환기는 1.2V 65nm 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 유효 칩 면적은 $0.87mm^2$, 1.2V 전원전압에서 약 110mW의 전력소모를 나타내었다. 측정 결과 샘플링 주파수 800MHz, 입력 주파수 250MHz에서 39.1dB의 SNDR 특성을 보여주었으며, offset self-calibration 회로를 사용 하지 않은 A/D 변환기에 비해 SNDR이 약 3 dB 향상되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.557-560
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• 2004

In this study, we design the one-chip PWM IC for SMPS (Switching Mode Power Supply) application. We determine the IC spec. and simulated each block of PWM IC (Reference, Error amp., Comparator, Oscillator) with Smart Spice (SILVACO Circuit Simulation Tool). Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain (${\simeq}65dB$), unity frequency (${\simeq}190kHz$) and large PM($75^{\circ}$).Saw tooth generators operate with 20K oscillation frequency (external resistor, capacitor).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.675-678
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• 1998

In this paper, power amplifiers for PCS phone were designed with the GEC Marconi H40 HEMT libray. The 1st stage was carefully designed in order to obtain k〉1 using a parallel resistor, and its S21 gain of 18.3dB and input reflection coefficient of -4dB were obtained. And S21 gain of 18dB and input reflection coefficient of -7dB were obtained from the 2nd stage. Finally, total S21 gain of 38dB, input reflection coefficient of -16dB, power gain of 35.2dB, output power of 28.7dBm and PAE(power added efficiency) of 29% were obtained from the designed MMIC power amplifiers. The chip size is $1.729$\times$0.94\textrm{mm}^2.$

• 전기전자학회논문지
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• 제11권1호통권20호
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.174-180
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• 2009

A new flexible electronics technology, named P-FCB (Planar Fashionable Circuit Board), is introduced. P-FCB is a circuit board technology implemented on the plain fabric patch for wearable electronics applications. In this paper, the manufacturing of P-FCB, and its electrical characteristics such as sheet resistance, maximum current density, and frequency characteristics are reported. The fabrication methods and their electrical characteristics of passive devices such as resistor, capacitor, and inductor in P-FCB are discussed. In addition, how to integrate silicon chip directly to the fabric for the flexible electronics system are described. Finally, examples of P-FCB applications will be presented.

• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology