• Journal of Chest Surgery
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• v.50 no.3
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• pp.153-162
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• 2017

Background: The mesenchymal-epithelial transition factor (MET) receptor can be overexpressed in solid tumors, including small cell lung cancer (SCLC). However, the molecular mechanism regulating MET stability and turnover in SCLC remains undefined. One potential mechanism of MET regulation involves the C-terminus of Hsp70-interacting protein (CHIP), which targets heat shock protein 90-interacting proteins for ubiquitination and proteasomal degradation. In the present study, we investigated the functional effects of CHIP expression on MET regulation and the control of SCLC cell apoptosis and invasion. Methods: To evaluate the expression of CHIP and c-Met, which is a protein that in humans is encoded by the MET gene (the MET proto-oncogene), we examined the expression pattern of c-Met and CHIP in SCLC cell lines by western blotting. To investigate whether CHIP overexpression reduced cell proliferation and invasive activity in SCLC cell lines, we transfected cells with CHIP and performed a cell viability assay and cellular apoptosis assays. Results: We found an inverse relationship between the expression of CHIP and MET in SCLC cell lines (n=5). CHIP destabilized the endogenous MET receptor in SCLC cell lines, indicating an essential role for CHIP in the regulation of MET degradation. In addition, CHIP inhibited MET-dependent pathways, and invasion, cell growth, and apoptosis were reduced by CHIP overexpression in SCLC cell lines. Conclusion: C HIP is capable of regulating SCLC cell apoptosis and invasion by inhibiting MET-mediated cytoskeletal and cell survival pathways in NCI-H69 cells. CHIP suppresses MET-dependent signaling, and regulates MET-mediated SCLC motility.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.615-616
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• 2008

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.140-143
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• 2004

Chemical mechanical polishing(CMP) is essential technology to secure the depth of focus through the global planarization of wafer. But a variety of defects such as contamination, scratch, dishing, erosion and corrosion are occurred during CMP. Especially, dishing and erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the life time of the semiconductor. Due to this dishing and erosion must be prohibited. The pattern density and size in chip have a significant influence on dishing and erosion occurred over-polishing. Decreasing of abrasive concentration results in advanced pattern selectivity which can lead the uniform removal in chip and decrease of over-polishing. The fixed abrasive pad was applied and tested to reduce dishing and erosion in this paper. Consequently, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with proposed fixed abrasive pad and chemicals.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.38-45
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• 2005

Chemical mechanical polishing(CMP) has been widely accepted for the planarization of multi-layer structures in semiconductor fabrication. But a variety of defects such as abrasive contamination, scratch, dishing, erosion and corrosion are occurred during CMP. Especially, dishing and erosion defects increase the metal resistance because they decrease the interconnect section area, and ultimately reduce the lift time of the semiconductor. Due to this reason dishing and erosion must be prohibited. The pattern density and size in chip have a significant influence on dishing and erosion occurred by over-polishing. The fixed abrasive pad(FAP) was applied and tested to reduce dishing and erosion in this paper. The abrasive concentration decrease of FAP results in advanced pattern selectivity which can lead the uniform removal in chip and declining over-polishing. Consequently, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with proposed FAP and chemicals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.791-797
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• 2001

In this paper, high-speed ,large-capacity ATM switching-chip is developed by MCM technology. MCM technology is suited for light-weight portable communications, mobile computing, high-frequency applications. For test of the developed MCM switching-chips, the simulating model is made by VHDL code of previously developed chip and input-output values of modeling pattern are obtained through the simulation. After the pattern values in chip-test machine are inserted , their results are compared with the simulation results. The design in this paper is simulated by synopsys design tool using SUN workstation and functions of chip is measured by TRILLIUM machine. Simulated and measured results have been compared, showing close agreement. Last, the MCM technique presented in this paper will provide useful insight into future designs.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1069-1072
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• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.2
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• pp.130-135
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• 2005

In this papers, we made study for plastic chip antenna, the plastic is Foamex with the circle of PVC and its electric characteristics are dielectric constant 1.9, insulation intensity 112 KV/cm. The proposed antenna is same as the conventional antennas are usually constructed with ceramic chip, which are not fragile in nature and don't tend to break easily. Therefore the proposed antenna with its advantage is attractive for application in mobile antenna. In order to valid the proposed papers, it is implemented the antennas of four types and experimented. From the results, we conformed that the antennas are operated at the dual band which is cellular band and Korea-PCS band. And the gain of the antennas has about above -2 dB and the pattern is same as conventional antennas. From this papers, the realized antennas using Foamex material will be application for mobile phone antenna.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.191-197
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• 2005

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1115-1122
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• 2003

In this paper we fabricated microchip antenna operating in bluetooth frequency bands(2.402∼2.480GHz). The antenna has a size of about 54mm${\times}419mm${\times}40.8mm, giving a total bluetooth PCB for support and chip of about 11mm${\times}44mm${\times}41.6mm. Bandwidth of the designed and fabricated chip antenna for bruetooth is 10.71 % at the resonated frequency of 2.45GHz and the resonant frequency and bandwidth versus change of any arbitrary feed point is observed. also, E-plane and H-plane in the Measured radiation pattern characteristic of chip antenna is compared and analyzed.