• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.76-82
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• 1998

As the minimum feature size of a semiconductor chip gets smaller, the inevitable distortion of patterned image by optical lithography becomes the limiting factor in the mass production of VLSI. The optical proximity correction (OPC), which corrects pattern distortion that originates from the resolution limit of optical lithography, is becoming indispensable technology. In this paper, we describe a program that corrects optical proximity effect and thus finds the optimum mask pattern with a Monte-Carlo method. The program was applied to real memory cell patterns to produce mask patterns that generate image patterns closer to object images than original mask patterns, and increase of process margin is expected, as well.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.435-442
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• 2018

This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.3
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• pp.248-251
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• 2009

We have investigated the effect of the quality of 1.3 um distributed feed back laser diode (DFB-LD) on the design of anti-reflection (AR) coatings. Optimal condition of AR coating to prevent internal feedback from both facets and reduce the reflection-induced intensity noise of laser diode was simulated with Macleod Simulator. Coating materials used in this work were ${Ti_3}{O_5}$ and $SiO_2$, of which design thickness were 105 nm and 165 nm, respectively. AR coating films were deposited by Ion-Assisted Deposition system. The electrical and optical properties of 1.3 um laser diode were characterized by Bar tester and Chip tester. Threshold current and slop-efficiency of DFB-LD were 27.56 mA 0.302 W/A. Far field pattern and wavelength of DFB-LD were $22.3^{\circ}(Horizontal){\times}24.4^{\circ}$ (Vertical), 1313.8 nm, respectively.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.1
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• Design & Manufacturing
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• v.2 no.1
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• pp.45-50
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• 2008

Micro channel is to fabricate desired pattern on the polymer substrate by pressing the patterned mold against the substrate which is heated above the glass transition temperature, and it is a high throughput fabrication method for bio chip, optical microstructure, etc. due to the simultaneous large area patterning. However, the bad pattern fidelity in large area patterning is one of the obstacles to applying the hot embossing technology for mass production. In the present study, stamper of cross channel with width $100{\mu}m$ and height $50{\mu}m$ was manufactured using UV-LiGA process. Micro channel was manufactured using stamper manufactured in this study. Also replicability appliance was evaluated for micro channel and factors affected replicability were investigated using Taguchi method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.308-314
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• 2006

A line scan camera is applied to enhance COG(Chip On Glass) inspection accuracy to be measured a few micro unit. The foreign substance detection among various faulty factors has been the most difficult technology in the faulty automatic inspection step since COG pattern is very miniature and complexity. In this paper, we proposed two step area segmentation template matching method to increase matching speed. Futhermore to detect foreign substance(such as dust, scratch) with a few micro unit, the new method using gradient mask and AND operation was proposed. The proposed 2 step template matching method increased 0.3 - 0.4 second matching speed compared with conventional correlation coefficient. Also, the proposed foreign substance applied masks enhanced $5-8\%$ faulty detection rate compared with conventional no mask application method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.1
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• pp.8-15
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• 2021

Micro-LEDs can be applied to various parts of a product. However, it has disadvantages compared to general LEDs in large displays such as low efficiency, intensity, and contrast ratio, among others, owing to their short history of study. The simulations were carried out using ray-tracing software to investigate the change in light intensity and light distribution according to pattern shapes on the sapphire substrate of the flip-chip micro-LED (FC μ-LED) array. Three patterns-concave square patterns, convex square patterns, and Ag coated convex patterns-which existed on the opposite side of FC μ-LEDs (115 ㎛ × 115 ㎛) array, were applied. The intensity of FC μ-LEDs on the center of the receivers depends on the pattern depth with shape. The concave square patterns having FC μ-LEDs arrays show that decreasing intensity as the patterns depth. On the contrary, the convex square patterns having FC μ-LEDs arrays shows that increasing intensity as the patterns depth. In addition, the highest intensity shows that FC μ-LEDs having Ag-coated convex patterns on the opposite side of sapphire lead to a reduction in light crosstalk owing to the Ag film.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.5
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• pp.98-107
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• 1995

The in-process detection of drill wear and breakage is one of the most importnat technical problems in unmaned machining system. In this paper, the monitoring system is developed to monitor abnormal drilling states such as drill breakage, drill wear and unstable cutting using motor current. Drill breakage is detected by level monitoring. Tool wear is classified by fuzzy pattern recognition. The key feature for classification of tool wear is the estimated flank wear which is calculated by the proposed flank wear model. The characteristic of the model is not sensitive to the variation of cutting conditions but is sensitive to drill wear state. Unstable cutting states due to the unsmooth chip disposal and the overload are monitored by the variance/mean ratio of spindle motor current. Variance/mean ratio also includes the information about the prediction of drill wear and drill breakage. The evaluation experiments have shown that the developed system works very well.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.7-15
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• 2006

In-situ observation of electromigration in thin film pattern of 63Sn-37Pb solder was performed using a scanning electron microscope system. The 63Sn-37Pb solder had the incubation stage of electromigration for edge movement when the current density of $6.0{\times}10^{4}A/cm^2$ was applied the temperature between $90^{\circ}C\;and\;110^{\circ}C$. The major diffusion elements due to electromigration were Pb and Sn at temperatures of $90-110^{\circ}C\;and\;25-50^{\circ}C$, respectively, while no major diffusion of any element due to electromigration was detected when the test temperature was $70^{\circ}C$. The reason was that both the elements of Sn and Pb were migrated simultaneously under such a stress condition. The existence of the incubation stage was observed due to Pb migration before Sn migration at $90-110^{\circ}C$. Electromigration behavior of 63Sn-37Pb solder had an incubation time in common for edge drift and void nucleation, which seemed to be related the lifetime of flip chip solder bump. Diffusivity with $Z^*$(effective charges number) of Pb and Sn were strongly affect the electromigration-induced major diffusion element in SnPb solder by temperature, respectively.