• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.37-42
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• 2011

In this paper, novel carbon nanotube (CNT)-filled Solderable electrically conductive adhesive (ECA) and joining process have been developed. To investigate the bonding characteristics of CNT-filled Solderable ECA, three types of Solderable ECAs with different CNT weight percent (0, 0.1, 1wt%) were formulated. For a joining process, the quad flat package (QFP) chip was used. The QFP chip had a size of $14{\times}14{\times}2.7$ mm and a 1 mm lead pitch. The test board had a Cu daisy-chained pattern with 18 ${\mu}m$ thick. After the bonding process, the bonding characteristics such as morphology of conduction path, electrical resistance and pull strength were measured for each formulated ECAs. As a result, the electrical and mechanical bonding characteristics for a QFP joints using CNT-filled ECA were improved about 10% compared to those of QFP joints using ECA without CNT.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.75-80
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• 2013

According to advance of electronic packaging technology, electronic package becomes smaller. Miniaturization of package causes the temperature rise of package. This can degrade life of electronic device and generate the failure of electronic system. In this study, we proposed a new semi-embedded structure with micro pattern for maximizing heat dissipation. A proposed structure showed the characteristics which have maximum temperature lower than $20^{\circ}C$ compared with conventional structure. And also, in view of thermal stress and strain, our structure showed a remarkably low value compared with other ones. We expect that the new structure proposed in this work can be applied to an flip-chip package of the future.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.383-390
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• 2014

This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical synapse model. In order to fabricate using a 0.18 um CMOS standard process technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This full-chip integration minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. The experimental results demonstrate that the proposed excitatory CMOS neuron oscillator performs the expected waveforms with scaled time and amplitude. The active silicon area of the fabricated chip is $1.1mm^2$ including I/O pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.625-632
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• 2002

In this paper, a wide band modified inverted-F type antenna printed on a high dielectric ceramic material is designed and fabricated. This antenna is designed to have optimum antenna characteristics analyzing the effects of design parameters such as printed antenna pattern, ceramic dielectric material dimension and dielectric constant on antenna characteristics using the commercial simulation tool HFSS. The fabricated antenna's width, length and height are 8 mm, 8 mm and 3 mm, respectively. Measurement results show that it has -10 dB bandwidth of 270 MHz which satisfies the IMT-2000 bandwidth required for handset and that its maximum radiation gain is 2 dBi.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.281-287
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• 1998

$BiNbO_4$ ceramics doped with 0.07wt% $V_2O_5$ and 0.03wt% CuO (BNC3V7) were sucessfully sintered at $900^{\circ}C$ through the firing process with Ag electrode. The BNC3V7 shows typically Dielectric constant of 44.3, Thermal Coefficient of resonance Frequency(TCF) of 2 ppm/$^{\circ} and $Qxf_o$ value of 22,000 GHz. The laminated chip Low Pass Filter (LPF) is very sensitive to chip processing parameters, was confirmed by the computer simulation as a function of Q(Quality factors), filter size, capacitor layer thickness, inductor pattern widths. The multilayer type LPF was fabricated by screen-printing with Ag electrode after tape casting and then compared with the simulated characteristics. The results show that characterization of band pass width was similar to that of designed ones.

• Journal of Navigation and Port Research
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• v.33 no.1
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• pp.51-56
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• 2009

This paper presents the design of high sensitive/broadband tag antenna for Radio Frequency Identification (RFID) in Ultra High Frequency(UHF) band. A proposed tag antenna size is $60\;mm\;{\times}\;10\;mm\;{\times}\;1\;mm$. The resonant frequency is 910MHz and bandwidth is about 900 MHz at -10 dB below. The measured return loss and directional pattern have been confirmed a good agreement with the calculation results. The read range of proposed tag antenna with chip is observed about 6.5 m and proposed tag antenna has been observed an average 0.5 m for more than read range of the commercial tag antenna.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.2
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• pp.154-160
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• 2009

This paper describes a wide bandwidth RFID tag antenna design for protection of connection part between chip and antenna. A proposed tag antenna size, a resonant frequency and bandwidth are $53{\times}10{\times}1\;mm$, 900 MHz and 800 MHz($500{\sim}1,300\;MHz$) at -10 dB below, respectively. The dielectric materials with different relative permittivity such as polyethylene, glass and silicon were applied for protection of connection part between the proposed antenna and chip on the way of whole and partial housing. The measured return loss and radiation pattern agreed well with the calculation results. The read range of the proposed tag antenna without any housing and of tag antenna with housing covered over all by silicon with 3 mm thickness were observed about 5 m and 4 m, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1541-1547
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• 2005

In this paper, Dualband internal antenna for GSM/DSC handset is proposed. The antenna has a size of about $38mm{\times}90mm{\times}1mm$, giving a total mobile phone PCB for support and fold type patch of about $30mm{\times}8mm{\times}3.2mm$. This antenna characteriatic facilitates the fine-tuning of the two operating frequencies of 909MHz and 1762MHz in the dualband design. The measured radiation pattern in the E-plane and H-plane for operating frequencies of 909MHz and 1762MHz is compared and analyzed. The designed and fabricated two band internal antenna for GSM/DSC handset have a gain between 0dBi and 2.0dBi at all bands. Also, the electric firld distribution and directivity on human head caused by portable phone is analyzed. An analysis model is composed of a human head model and the antenna mounted on the same ground plane as portable telephone size.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.80-85
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• 2010

BGA 409 chip currently the most as a visual inspection of the exterior inspection is conducted. Human depending on visual inspection of the exterior inspection of the current state of testers, depending on how the test results because the change is difficult to expect reliable results. Therefore, the challenges of visual inspection of BGA solder balls to improve the visual inspection technique was developed. However, BGA solder ball size of the microstructure and the characteristics of the distinction between hard test the accuracy of the fall orientation error has a problem. In this paper BGA solder balls exterior inspection of the accuracy to improve the edge detection algorithm, the complement of features and only the comparison proposed a pattern-matching techniques, based on the characteristics of spatial configuration of the area by improving the standard error of the orientation proposed improvements.