• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.10
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• pp.112-118
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• 2021

In this study, an inspection method using a color image is proposed to conduct a real-time inspection of covalent organic framework (COF) films to detect defects, if any. The COF film consists of an upper pattern SR and a lower PI. The proposed system detects the defects of more than 20 ㎛ on the SR surface owing to the characteristics of the pattern, whereas on the PI surface, it detects defects of more than 4 ㎛ by utilizing a micro-optical system. In the existing system, it is difficult for the operator to conduct a full inspection through a high-performance microscope. The proposed inspection algorithm performs the inspection by separating each color component using the color contrast of the pattern on the SR side, and on the PI surface it inspects the bonding state of the mounted chip. As a result, it is possible to confirm the exact location of the defects through the SR and PI surface inspections in the implemented inspection.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• The Journal of the Acoustical Society of Korea
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• v.36 no.2
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• pp.123-129
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• 2017

In this paper, the realization of a directional digital hearing aid was considered. Conventional time domain time delay method was replaced with digital filters in order to make any general-purposed DSP (Digital Signal Processing) chip to produce the similar directivity pattern. Both the time delay algorithm and the digital filter algorithm were initially evaluated by Matlab (Matrix laboratory) for comparison, and it was confirmed by CSR 8675 Bluetooth DSP IC (Digital Signal Processing Integrated Circuit) chip firmware realization. Some remote control features by a smart phone was added to the smart hearing aid for user interface easiness.

• Journal of IKEEE
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• v.20 no.2
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• pp.163-166
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• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• Journal of KIISE:Software and Applications
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• v.31 no.6
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• pp.792-798
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• 2004

In this paper, we will introduce a new corner detector for the wafer die position recognition. The die position recognition procedure is necessary for WSCSP(Wafer Scale Chip Scale Packaging) technology, decide the accuracy of post-procedure. We present a hierarchical gray level corner detection method for the recognition of the die position from a wafer image. The new corner detector divides the corner region into many homocentric circles, and calculates the comer response and the angle of direction about each circle to get an accurate toner point. The new corner detector has a hierarchical structure so it can detect comer point more quickly than general gray level corner detector.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.89-91
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• 2003

The determination of DNA hybridization reaction can apply the molecular biology research, clinic diagnostics, bioengineering, environment monitoring, food science and other application area. So, the improvement of DNA detection system is very important for the determination of this hybridization reaction. In this study, we report the characterization of the probe and target oligonucleotide hybridization reaction using the evanescent field microscopy. First, we have fabricated DNA chip microarray. The particles which were immobilized oligonucleotides were arranged by the random fluidic self-assembly on the pattern chips, using hydrophobic interaction. Second, we have detected DNA hybridization reaction using evanescent field microscopy. The 5'-biotinylated probe oligonucleotides were immobilized on the surface of DNA chip microarray and the hybridization reaction with the Rhodamine conjugated target oligonucleotide was excited fluorescence generated on the evanescent field microscopy. In the foundation of this result, we could be employed as the basis of a probe olidonucleotide, capable of detecting the target oligonucleotide and monitoring it in a large analyte concentration range and various mismatching condition.

• Proceedings of KOSOMES biannual meeting
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• 2005.11a
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• pp.203-208
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• 2005

The CGO (Chip on Glass) to be measured a few micro unit is captured by line scan camera for the accuracy of chip inspection. But it is very sensitive to scan speed and lighting conditions. In this paper, we propose the methods to increase the accuracy of faulty detection by image subtraction. Image subtraction is detected faultiness by subtracting the image of a ' perfect ' COG from trot of the sample under tests. For image subtraction to be successful, the two images must be pre챠sely registered The two images is registered by the area segmentation pattern matching, and the result image get by operating the gradient mask image and the image to practice subtraction. A series of experimentation showed that the proposed algorithm shows substantial improvement over the other image subtraction methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.106-113
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• 2014

Recently, to reduce test cost by efficiently compressing test patterns for SOCs(System-on-a-chip), different compression techniques have been proposed including the FDR(Frequency-directed run-length) algorithm. FDR is extended to EFDR(Extended-FDR), SAFDR(Shifted-Alternate-FDR) and VPDFDR(Variable Prefix Dual-FDR) to improve the compression ratio. In this paper, a frequency-ordered modification is proposed to further augment the compression ratios of FDR, EFDR, SAFRD and VPDFDR. The compression ratio can be maximized by using frequency-ordered method and consequently the overall manufacturing test cost and time can be reduced significantly.

• Journal of KSNVE
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• v.9 no.3
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• pp.477-484
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• 1999

This study aims to present proper thickness of resilient mount and pattern of chips for the improvement of impact sound isolation. To achieve this aim, field tests were performed to evaluate the performance of impact sound isolation of pilot samples using waste tire chips against light and heavy-weight impacter, which samples were installed over concrete slabs of an apartment housing. In this study, the experiments were performed by the impact sound level of floors in KS F 2810 "Method for field measurement of floor impact level". As results, a flooring structure using waste tire chips as a resilient mount, with no relation to chip's types, has enhanced performance by 1~2 degree in light impact sound isolation, while it has improvement in heavy impact sound isolation. And fiber-type chips have better performance than granule-type ones when they overlaid concrete slab with 15~20 mm of thickness. For the improvement of impact sound isolation, it is recommended that insulating materials should be applied at joints between floating floors and walls, or floating floors and a doorframes, and also waterproof papers should be used for the effective thickness of resilient mount.ent mount.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.126-129
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• 2003

The electrical properties of a ZnO-based multilayered chip varistor (abbreviated as MLV) were studied as functions of firing condition and the degree of lamination. The fundamental varistor characteristics such as nonlinear coefficient and breakdown voltage were independent of the degree of lamination. As the number of the laminated ceramic sheets increased, however, not only the energy handling capability but also the capacitance and the leakage current which are relevant to delayed response to the voltage surge and the pre-breakdown energy loss, respectively, increased. With the increase of firing temperature between $950^{\circ}C$ and $1150^{\circ}C$, both the capacitance and the leakage current of the MLV increased due mainly to the grain growth of ZnO and the volatilization of $BiO_2O_3$. High performance MLVs with clear electrode pattern were obtained at the firing temperature range of $l000{\sim}1050^{\circ}C$ in this experiment.