1 |
Chandra, A, Chakrabarty, K, "Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression" VLSI Test Symposium, IEEE VTS 2001.
|
2 |
Shyue-Kung Lu, Hei-Ming Chuang, Guan-Ying Lai, Bi-Ting LaiYa-Chen Huang, "Efficient Test pattern Compression Techniques Based on Complementary Huffman coding" IEEE Circuits and Systems International Conference. ICTD 2009.
|
3 |
Chandra. A, Chakrabarty. K, "System-on-a-chip test-data compression and decompression architectures based on Golomb codes" IEEE Trans, Computer-Aided Design of Integrated Circuits and Systems, Vol, 20, pp. 355-368, Mar 2001.
DOI
ScienceOn
|
4 |
El-Maleh, A.H. "Test data compression for system-on-a-chip using extended frequency -directed run-length code", Computers & Digital Techniques, IET, Vol. 2, pp. 155-163, May 2008.
|
5 |
Chandra. A, Chakrabarty. K, "Reduction of SOC test data volume, scan power and testing time using alternating run-length codes", Design Automation Conference, 2002. Proceedings. 39th,
|
6 |
Laung-Terng Wang, Xiaqing Wen and Shianling Wu, "Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains" IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 229-312, Feb 2010.
|
7 |
Xtysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos, "Optimal Selective Huffman Coding for Test-Data Compression," IEEE Trans. on Computer, Vol. 56, no. 8, pp. 1146-1152, August 2007.
DOI
ScienceOn
|
8 |
Yang Yu, Zhiming Yang, Xiyuan Peng, "Test Data Compression Based on Variable Prefix Dual-Run-Length Code", IEEE International I2MTC, pp. 2537-2542, May 2012.
|