• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of the Korean Wood Science and Technology
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• v.43 no.3
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• pp.381-389
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• 2015

In this study, the effects of moisture content and particles size of ground particles of torrefied larch chips on the pelletizing process were investigated depending on torrefaction conditions ($220^{\circ}C$-50 min, $250^{\circ}C$-50 min, $250^{\circ}C$-120 min). The moisture content in the torrefied chip decreased to 0.69~1.75%, while ash content and calorific value increased compared to untreated chip. In addition, weight loss significantly increased during torrefaction due to hemicellulose degradation. The carbon content in torrefied larch chip increased compare to untreated larch chip, while the hydrogen and oxygen contents decreased. The lignin and glucan contents in torrefied larch chip increased with increasing severity of the torrefaction condition, while hemicellulose decreased. In the particle size distribution of ground particles of torrefied larch chip, larch torrefied at severe conditions was found to produce smaller particles (~1 mm) than that of the larch torrefied at mild conditions. Macropore (over $500{\AA}$) in the torrefied particle was produced during torrefaction. During the pelletizing using ground particles of torrefied larch chip, the pressure needed in pelletizing decreased and pellet length increased with increasing moisture content, regardless of the particle size.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.6
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• pp.5-11
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• 2003

The number of the enterprises which utilize network technology has been increasing for solving problems such as productivity improvement, market trend analysis, and material collection for making decision. Especially, the management of equipment and the recovery time reduction when machines break down are very important factors in productivity improvement of the enterprise. Currently, most of the remote trouble diagnosis of equipment using the internet have just one function of transmitting the trouble information to the user. Therefore it does not directly reflect the user's recovery experience or the developer's new recovery methods. If the user's experienced recovery methods or the developer's recovery methods as well as the basic recovery methods are reflected online or on the internet, it makes it possible to recover faster than before. In this paper, we develop a Remote Monitoring Server (RMS) for chip mounters, and make it possible to reduce the recovery time by reflecting the user's experience and developer's new methods in addition to presenting the basic recovery methods. For this, trouble recovery concept will be defined. Based on this, many functions(trouble diagnosis, the presentation of the basic recovery methods, user's and developer's recovery method, counting function of the trouble number of each code, and presentation of usage number of each recovery methods) were developed. By utilizing the reports of the actual results of chip mounter and the notice function of the parts change time, the rate of operation of the chip mounter can be improved.

• Geomechanics and Engineering
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• v.37 no.5
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• pp.443-452
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• 2024

The use of sand-tire chip mixtures in construction industry is a sustainable and environmentally friendly approach that addresses both waste tire disposal and soil improvement needs. However, the addition of tire chip particles to natural soils decreases maximum shear modulus (G_max), but increases compressibility, which can be potential drawbacks. This study examines the effect of overconsolidation stress history on the maximum shear modulus (G_max) of rigid-soft mixtures with varying size ratios (SR) and tire chip contents (TC) by measuring the wave velocity through a 1-D compression test during loading and unloading. The results demonstrate that the G_max of tested mixtures in the normally consolidated state increased with increasing SR and decreasing TC. However, the tested mixtures with a smaller SR exhibited a greater increase in G_max during unloading because of the active pore-filling behavior of the smaller rubber particles and the consequent increased connectivity between sand particles. The SR-dependent impact of the overconsolidation stress history on G_max was verified using the ratio between the swelling and compression indices. Most importantly, this study reveals that the excessive settlement and lower G_max of rigid-soft mixtures can be overcome by introducing an overconsolidated state in sand-tire chip mixtures with low TC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.37-41
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• 2014

One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1095-1101
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• 1999

Electroless Ni plating is applied to form bumps and UBM layer for flip chip interconnection. Characteristics of electroless Ni are also investigated. Zincate pretreatment is analyzed and plated layer characteristics are investigated according to variables like temperature, pH and heat treatment. Based on these observations, characteristics dependence to each variables and optimum electroless Ni plating conditions for flip-chip interconnection are suggested. Electroless Ni has 10wt% P, $60\mu\Omega$-cm resistivity, 500HV hardness and amorphous structure. It changes crystallized structure and hardness increases after heat treatment After interconnection of electroless Ni bumps by ACF flip chip method, we show their advantages and possibility in microelectronic package applications.

• Journal of Platform Technology
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• v.8 no.1
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• pp.24-32
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• 2020

This paper designed and manufactured a chip mounter based on 3D printer technology that can be used for educational research or sample production to disseminate chip mounter, a core technology of SMT line. A stepper motor with open loop control is used for low cost drive design. The shortcomings of the motor's vibration and disassembly caused by the use of the step motor were compensated by the Micro-Step control method. In the chip mounter experiment, the gerber file was generated on the small chip mounter, printed at the actual size, and the solder cream was printed on the HASL-treated PCB in the same manner as the sample board fabrication. As a result of the experiment, unlike the 2012 micro components, parts such as SOIC and TQFP that require correction are twice as long as the component mounting time, but it can be confirmed that they are mounted relatively accurately. In addition, as a result of repeatedly measuring the error of the initial position 10 times, it was confirmed that a relatively small error of about 0.110mm occurs.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.65-71
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• 2016

Bluetooth technology(BT) is a standard for short distance wireless communication and widely used to connect and control various electronic and telecommunication devices without wires, where CSR8670 chip is generally adopted. These BT devices are required to comply with BT specification and the equipments for conformance test are also important. However, the existing BT testing methods have inconvenience in that they are mostly time-consuming procedure due to not only repetitive execution for each evaluation element but also error-prone nature of manual experiments. This paper proposes an automated BT communication test method using CSR8670 chip, which solves the problems related to manual testing methods. The proposed method can reduce the development period of BT products and guarantee the quality improvement owing to the exact system error detection capability.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.