• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2450-2452
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• 2003

We present a method to increase the productivity of multihead-gantry chip mounters for PCB assembly lines. To minimize the assembly time, we generate the mount sequence using the genetic algorithm. The chromosome, fitness function, and operators are newly defined to apply the algorithm. Simulation results are presented to verified the usefulness of the method.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.51-69
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• 2001

Japan Jisso Technology Roadmap 2001 (JJTR2001) was published by JEITA in April 2001. Future electronic products request further higher assembly technology (ex. Finer pitch packages & components, 3D assembly, etc.) to reduce size and improve performance of the electric products. For LSI Packages, finer ball pitch technology and finer chip connection technology will be developed. For electric components, further size reduction will be developed. For Jisso (assembly) machine, finer pitch assembly and short tact time technology will be developed. Mr. Utsunomiya will present PCB roadmap next.

• Transactions on Electrical and Electronic Materials
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• v.13 no.3
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• pp.129-135
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• 2012

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.488-491
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• 2002

This growth if WWW(World Wide Web) with the spread of ADSL provides us with a variety of service that are the extensions of opportunities to get information. a various education methods by remote courses and electronic commerce. Remote Monitoring Server(RMS) that uses internet and WWW is constructed for chip mounter. Hardware base consists of RMS, chip mounter and C/S server. In this paper, we realize the remote management system with monitoring and diagnosis function to efficiently operate chip mounter the one of PCB assembly equipment. The remote management system for chip mounter consists of RMS(Remote Monitoring Server) and C/S server. RMS manages real-time information from chip mounter through TCP/IP. RMS that utilizes real-time information informs user of the actual output the operation status of chip mounter, user of the actual output, the operation status of chip mounter, the trouble code and the trouble description.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.45-61
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• 1999

General trend in electronics industry towards multimedia in the 21 century is presented here. All equipments require fast graphic processing together with thin and lightweight assembly technology. In Japan, CSP was developed and applied to mobile equipments for several years, and recently stacked die assembly technology is being developed. In addition, so-called flip chip technology is also being developed and which is applied to MCP and MCM little by little these days. Here current packaging technology in Japan is presented including above.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.24-38
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• 2009

In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.105-129
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• 2000

• Journal of the Korea Society for Simulation
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• v.26 no.1
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• pp.69-75
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• 2017

An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.