• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1117-1125
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• 2007

In this paper, a study has been performed on the design of small loop probe and analysis of induced electromagnetic wave signal from a smartcard for contactless cryptographic analysis. Probes for cryptographic analysis are different from conventional EM probes, because the purpose of proposed probe is to obtain the information for secret key analysis of cryptographic system. The waveform of induced voltage on probe must be very close to radiated waveform from IC chip on smartcard because electromagnetic attack makes an attempt to analyze the radiated waveform from smartcard. In order to obtain secret key information, we need to study about cryptographic analysis using electromagnetic waves, an approximate model of source, characteristic of probe for cryptographic analysis, measurement of electromagnetic waves and calibration of probes. We measured power consumption signal on a smartcard chip and electromagnetic wave signal using proposed probe and compared with two signals of EMA point of view. We verified experimently the suitability of the proposed small loop probe for contactless cryptographic analysis by applying ARIA algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.219-225
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• 2014

This paper describes an IC for Power Factor Correction. It can use electrical appliances which convert power from AC to DC. The power factor can be influenced not only phase difference of voltage and current but also sudden change of current waveform. This circuit enables current wave supplied to load by close to sinusoidal and minimum phase difference of voltage and current waveform. A self oscillated 10[kHz]~100[kHz] pulse signal converted to PWM waveform and it chops rectified full wave AC power which flows to load device. The multiplier and zero current detector circuit, UVLO, OVP, BGR circuits were designed. This IC has been designed and whole chip simulation use 0.5[um] double poly, double metal 20[V] CMOS process.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.88-95
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• 2004

Micro stepping method is adopted in order to eliminate effectively the resonant phenomena and to increase the positional resolution. Exist micro-step method by using Sinusoidal waveform, drive circuit is complex by using micro controller and ROM, it have fault on cost Increase. This paper proposed trapezoidal current wave form for simple control circuit and micro stepping method by using a low cost controller. This paper proposed method verify by using CPLD(EPM9320RC208-15) of low cost. This paper make experiment that comparison of exist method and proposed method. This paper obstruct a escape of motor by using high speed detect.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.31-38
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• 2011

With the increasing demand for high-speed transmission systems, adaptive equalizers have been widely used in receivers to overcome the limited bandwidth of channels. In order to reduce the cost for testing high-speed receiver chips, on-chip eye-opening monitoring (EOM) technique which measures the eye-opening of data waveform inside the chip can be employed. In this paper, a 10-Gb/s adaptive 2-tap look-ahead decision feedback equalizer (DFE) with EOM function is proposed. The proposed EOM circuit can be applied to look-ahead DFEs while existing EOM techniques cannot. The magnitudes of the post-cursors are measured by monitoring the eye of received signal, and coefficients of DFE are calculated using them by proposed adaptation algorithm. The circuit designed in 90nm CMOS technology and the algorithm are verified with post-layout simulation. The DFE core occupies $110{\times}95{\mu}m^2$ and consumes 11mW in 1.2V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.400-402
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• 1994

This paper presents a digital implementation of delta modulation Technique for Active Power Filters. Delta modulated scheme is to control the harmonic-compensating current indirectly by adjusting the capacitor voltage to be sinusoidal. The overall control system has two feedback loops. One is the outer propotional feedback for loop regulating the dc current of active filters and the other is the inner feedback loop for maintaining the ac current waveform to be sinusoidal, and have zero power factor angle(i.e. unity power factor). The characteristics of the proposed is investigated by digital simulation using ACSL and experimental results are obtained by TMS370C756 Single-Chip Microprocessor relative to analog delta modulation technique.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1161-1164
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• 1992

In this paper demonstrates the possibiity of utilising clamped mode - series resonant converter technology in the high frequency link inverter configuration. Main circuit of the proposed inverter is analyzed through circuit analys and waveform simulation. In control circuit PLL circuit and 8 bit single chip microcontroller is adopted, therefore flexibility and accuracy of control circuit is increased.

• Journal of Biomedical Engineering Research
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• v.15 no.3
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• pp.281-288
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• 1994

In this paper, a new decomposition method of the interference EMG signal using MAMDF filtering and digital signal processor. The efficient software and hardware signal processing techniques are employed. The MAMDF filter is employed in order to estimate the presence and likely location of the respective templates which may include in the observed mixture, and high-resolution waveform alignment is employed in order to provide the optimal combination set and time delays of the selected templates. The TMS320C25 digital signal processor chip is employed in order to execute the intensive calculation part of the software. The method is verified through a simulation with real templates which are obtain ed from needle EMG. As a result, the proposed method provides an overall speed improvement of 32-40 times.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.670-672
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• 2004

In this paper, single phase boost converter with low current harmonic components and high power factor are proposed. A single-phase half-bridge rectifier based on a neutral point switch clamped scheme is proposed to draw a nearly unity power factor and regulate the DC link voltage. Three power switches are employed in the proposed rectifier. This rectifier is controlled to generate a bipolar or unipolar PWM voltage waveform on the AC side. The proposed converter is implemented by a digital signal processor.