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Design of 10-Gb/s Adaptive Decision Feedback Equalizer with On-Chip Eye-Opening Monitoring  

Seong, Chang-Kyung (Department of Electrical and Electronic Engineering, Yonsei University)
Rhim, Jin-Soo (Department of Electrical and Electronic Engineering, Yonsei University)
Choi, Woo-Young (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.1, 2011 , pp. 31-38 More about this Journal
Abstract
With the increasing demand for high-speed transmission systems, adaptive equalizers have been widely used in receivers to overcome the limited bandwidth of channels. In order to reduce the cost for testing high-speed receiver chips, on-chip eye-opening monitoring (EOM) technique which measures the eye-opening of data waveform inside the chip can be employed. In this paper, a 10-Gb/s adaptive 2-tap look-ahead decision feedback equalizer (DFE) with EOM function is proposed. The proposed EOM circuit can be applied to look-ahead DFEs while existing EOM techniques cannot. The magnitudes of the post-cursors are measured by monitoring the eye of received signal, and coefficients of DFE are calculated using them by proposed adaptation algorithm. The circuit designed in 90nm CMOS technology and the algorithm are verified with post-layout simulation. The DFE core occupies $110{\times}95{\mu}m^2$ and consumes 11mW in 1.2V supply voltage.
Keywords
Equalizer; decision feedback equalizer; adaptation; eye-opening monitoring;
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1 Yasumoto Tomita, et al., "A 10-Gb/s Receiver With Series Equalizer and On-Chip ISI Monitor in 0.11-m CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 986-993, Apr. 2005.   DOI
2 Jaeha Kim, et al., "Equalizer Design and Performance Trade-offs in ADC-based Serial Links," Custom Integrated Circuits Conf., Sep. 2010, invited paper
3 Jian-Hao Lu and Shen-Iuan Liu, "A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology," IEEE Trans. Circuit and Systems, vol. 56, no. 10, pp. 783-787, Oct. 2009.
4 Chih-Fan Liao and Shen-Iuan Liu, "A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR," ISSCC Dig. Tech. Papers, pp. 100-101, Feb. 2008.
5 M. Kawai, H. Watanabe, T. Ohtsuka, and K. Yamaguchi, "Smart Optical Receiver With Automatic Decision Threshold Setting and Retiming Phase Alignment," J. Lightwave Technol., vol. 7. no. 11, Nov. 1989.
6 Koon-Lun Jackie Wong, Alexander Rylyakov, and Chih-Kong Ken Yang, "A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions," IEEE J. Solid-State Circuits, vol. 42, No. 4, pp. 881-888, Apr. 2007.   DOI
7 Azita Emami-Neyestanak, et al., "A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE," IEEE J. Solid-State Circuits, vol. 42, No. 4, pp. 889-896, Apr. 2007.   DOI
8 Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, "A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology," IEEE J. Solid-State Circuits, vol. 44, No. 4, pp. 1298-1305, Apr. 2009.   DOI
9 Behnam Analui, et al., "A 10-Gb/s Two-Dimensional Eye-Opening Monitor in 0.13-um Standard CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2689-2699, Dec. 2005.   DOI
10 Tobias Ellermeyer, et al., "A 10-Gb/s Eye-Opening Monitor IC for Decision-Guided Adaptation of the Frequency Response of an Optical Receiver," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1958-1963, Dec. 2000.   DOI
11 F. Buchali, S. Lanne, J. -P. Thiery W. Baumert, and H. Bulow, "Fast Eye Monitor for 10 Gbit/s and its Application for Optical PMD Compensation," Tech. Digest OFC, 2001, TuP5