• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.623-630
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• 2010

This paper presents the implementation and characteristic analysis of a drive system for a three-phase permanent magnet motor with independent excitation winding that is applicable for electric bicycles. The design features improves the phase current waveform, output power, and torque by using advance angle control. This adjusts the phase angle of each phase current in relation to back EMF. In addition, a DC-side PI current control is performed through PWM generation circuit using a low-cost one-chip microcontroller and a CPLD chip, resulting in reduced system costs. Finally, the validity of this control scheme for driving electric bicycles and output/torque improvement characteristics are verified through analysis and experimental results.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.245-253
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• 2020

The human body and nervous system transmit information through electric charges. After the electric charge transmits information to the brain, we can feel pain, numbness, comfort, and other feelings. Electric therapy is currently used widely in clinical practice because the field of examination is more representative of electrocardiogram, and in the field of treatment is more representative of electrotherapy. In this study, we design a system for neurophysiological therapy and conduct parameter calculation and model selection for the components of the system. The system is based on a discontinuous conduction mode (DCM) boost circuit, and controlled and regulated by a single-chip microcomputer. The system does not only have a low cost but also fully considers the safety of use, convenience of the human-computer interface, adjustment sensitivity, and waveform diversity in the design. In future, it will have strong implications in the field of electrotherapy.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.951-954
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• 1999

A direct digital frequency synthesizer is designed in full custom method using 0.65${\mu}{\textrm}{m}$ CMOS n-well technology The chip provides the capability of the parallel operation using up to 4 chips with an operation frequency of 440MHz. The generated waveform can be modulated by various modulation techniques such as QPSK, 256 . 64. 32 . 16 QAM and FM.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.27-33
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• 1993

This paper presents the &tal controller for driving high frequency voltage fed PWM inverter that carrier frequency is over 2OkHz.We analyzed the conventional PWM to select a proper PWM pattern. as the result, obtained PWM pattern of the controller in which asynchronus staircase sinusoidal waveform is used as reference signal, and variable carrier ratio method was used for PWM control. The PWM controller is designed by fully digital method. Especially, Thk proposed controller is consisted of 8 bit one-chip microprocessor and digital logic. the former is for arithmetic and data processing, and the latter is for PWM pattern synthesis. Therefore, The responsibility and controllability is improved. Also, Data processing capability is improved using proper program to output modulation index with 9 bits. Circuits configuration of digital controller are made up of one chip 8051 and EPLD, and its controllability is tested by operating voltage fed inverter. Harmonics and current waveform is evaluated and analyzed for the voltage fed inverter system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.6
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• pp.511-520
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• 2000

Ultrasonic pulse echo method comes to be difficult to apply to the multi-layered structure with very thin layer, because the echoes from the top and the bottom of the layer are superimposed. We can easily meet this problem when the silicon chip layer in the semiconductor is inspected by a SAM equipment using fairly low frequency lower than 20MHz by which severe attenuation in the epoxy mold compound of packaging material can be overcome. Conventionally, deconvolution technique has been used for the decomposition of superimposed UT signals, however it has disabilities when the waveform of the transmitted signal is distorted according to the propagation. In this paper, the wavelet transform based deconvolution(WTBD) technique is proposed as a new signal processing method that can decompose the superimposed echo signals with superior performances compared to the conventional deconvolution technique. WTBD method uses the wavelet transform in the pre-stage of deconvolution to extract out the common waveform from the transmitted and received signal with distortion. Performances of the proposed method we shown by through computer simulations using model signal with noise and we demonstrated by through experiments for the fabricated semiconductor sample with partial delamination at the top of silicon chip layer.

• Korean Journal of Metals and Materials
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• v.50 no.2
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.1012-1016
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• 1998

According to the adoption of inverter circuit topology for welding machine area, the improvement of welding performance can be achieved. However conventional CO2 inverter arc welding machine uses the constant voltage characteristics. So the metal transfer is performed under unoptimum condition in the sence of spatter generation. In this paper the new control algorithm is proposed for welding machine, which is the instantaneous output current control method using single chip microprocessor. But the optimum waveform of welding current is still uncertain, as a first step for figuring out the optimized waveforms, this study was performed. And as a result of performance test of the proposed system, it was demonstrated that all of the waveform variation parameter could be set individually and the generated spatter is reduced compared to conventional inverter arc welding machine.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.427-430
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• 2005

A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.