• Journal of the Korean Ceramic Society
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• v.28 no.9
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• pp.675-682
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• 1991

Among many problems that need to be solved in the process of preparing multilayer chip LC filters, we studied the control of shrinkage in order to prevent the crack, warpage, and/or delamination which occurs at the interface between the inductance (L part) and the capacitance (C part). Shrinkage was controlled by compositions, powder size, calcining temperature and amount of organic binder. Capacitance sheet was prepared by mixing 65 wt% binder with the composition of 96 wt% TiO2 having an average particle size of 0.5 $\mu\textrm{m}$, 3 wt% CuO. After small amount of MnO2 and SiO2 added, it was calcined at 750$^{\circ}C$ for 2 hr. Inductance sheet was prepared by mixing 60 wt% binder with the composition of 49.5% mol% Fe2O3, 20.5 mol% ZnO, 20 mol% NiO and 10 mol% CuO which was calcined at 775$^{\circ}C$ for 2 hr. These sheets was laminated at 250 kg/$\textrm{cm}^2$, and cofired at 900$^{\circ}C$ for 2 hr to give rise to a multilayer chip LC filter without any warpage.

• Electrical & Electronic Materials
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• v.10 no.5
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• pp.492-499
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• 1997

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.1-11
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• 1981

This paper proposes a method of generalizing the clocking scheme in the Switched Capacitor Filter(SCF) design using Voltage Inverter Switches (VIS's). Parallel RC and RL elements, and parallel LC resonators can be implemented by the proposed clocking schemes Applying these new elements and the generalized clocking schemes to the SCF design, the total number of required operational amplifiers and capacitors can be reduced. Experimental results of a band- stop filter and a low-pass filter using a new type grounded VIS show good agreements with t he theoretical characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.873-877
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• 2007

In order to apply a complex multilayer chip LC filter, this study has estimated the interfacial reaction and coupling properties of dielectric materials $Pb(Fe_{1/2}Nb_{1/2})O_3$ and Ni-Zn-Cu ferrite materials through low-temperature co-sintering (LTCS). PFN powders were fabricated using double calcinated at $700^{\circ}C$ and then $850^{\circ}C$. While the perovskite phase rate was found to be 91 %, after heat treatment at $900^{\circ}C$ for 6h, the perovskite phase rate and density exhibited a value of 100 % and 7.46$g/cm^3$, respectively. The PFN/Ni-Zn-Cu ferrite, PFN/CUO (or $Pb_2Fe_2O_5$) and ferrite/CuO (or $Pb_2Fe_2O_5$) were mechanically coupled through interfacial reactions after the specimen was co-sintered at $900^{\circ}C$ for 6 h. No intermediate layer exists for the mutual coupling reaction. This result indicates the possibility of low-temperature co-sintering without any interfacial reaction layer for a multilayer chip LC filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.49-58
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• 1999

This paper describes an integrated low pass filter fabricated by using $0.8{\mu}m$ single poly CMOS ASIC technology. The filter has been designed for a 5th-order elliptic switched capacitor filter with cutoff frequency of 5khz, 0.1dB passband ripple. The filter consists of MOS swiches poly capacitors and five CMOS op-amps. For the realization of the SC filter, continuous time transfer function H(s) is obtained from LC passive type, and transfered as discrete time transfer H(z) through bilinear-z transform. Another filter has been designed by capacitor scaling for reduced chip area, considering dynamic range of the op-amp. The test results of two fabricated filters are cutoff frequency of 4.96~4.98khz, 35~38dB gain attenuation and 0.72~0.81dB passband ripple with the ${\pm}2.5V$power supply clock of 50KHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.4
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• pp.59-64
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• 2009

In this paper, we represent characteristics and equivalent circuit of donut type resonator of defected ground structure (DGS), and can control resonant frequency with chip capacitor. In General, DGS operates like with parallel LC resonator. We found out variation of resonance frequency when capacitor is placed on slot of DGS. If the chip capacitor replace with varactor diode, the resonance frequencies can be controlled by voltage. This tualable resonator can apply to voltage controlled oscillator and tunable bandpass filter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.620-626
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• 2015

In this paper, a 2~6 GHz wideband GaN power amplifier MMIC is designed and fabricated using a second-order all-pass filter for input impedance matching and an LC parallel resonant circuit for minimizing an output reactance component of the transistor. The second-order all-pass filter used for wideband lossy matching is modified in an asymmetric configuration to compensate the effect of channel resistance of the GaN transistor. The power amplifier MMIC chip that is fabricated using a $0.25{\mu}m$ GaN HEMT foundry process of Win Semiconductors, Corp. is $2.6mm{\times}1.3mm$ and shows a flat linear gain of about 13 dB and input return loss of larger than 10 dB. Under a saturated power mode, it also shows output power of 38.6~39.8 dBm and a power-added efficiency of 31.3~43.4 % in 2 to 6 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.351-354
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• 2006

Recently, a fuel cell with low voltage and high current output characteristics is remarkable for new generation system It needs both a DC-DC step-up converter and DC-AC inverter to be used in fuel cell generation system Therefor, this paper, consists of an isolated DC -DC converter to boost the fuel cell voltage 380[$V_{DC}$] and a PWM inverter with LC filter to convent the DC voltage to single phase 220[$V_{AC}$]. Expressly, a tapped inductor filter with freewheeling diode is newly implemented in the output filter of the proposed high frequency isolated ZVZCS PWM DC-DC converter to suppress circulating current under the wide output voltage regulation range, thus to eliminate the switching and transformer turn-on/off over-short voltage or transient phenomena Besides the efficiency of 93-97[%]is obtained over the wide output voltage regulation ranges and load variations.