• The Journal of the Acoustical Society of Korea
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• v.40 no.4
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• pp.370-381
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• 2021

This paper presented an efficient transceiver structure of multiband Frequency Shift Keying (FSK) signals with direct sequence spread spectrum for maintaining covertness and performance. In aspect to covertness, direct sequence spread spectrum method, which multiplying by Pseudo Noise (PN) codes whose rate is much higher than that of data sequence, is employed. In aspect to performance, in order to overcome performance degradation caused by multipath and Doppler spreading, we applied multiband, turbo equalization, and weighting algorithm are applied. Based on the simulation results, by applying 4 number of multiband and number of chips are 8 and 32, experiments were conducted in a lake with a distance of moving from 300 m to 500 m between the transceivers. we confirmed that the performance was improved as the number of bands and chips are increased. Furthermore, the performance of multiband was improved when the proposed weighting algorithm was applied.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.991-997
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• 2004

In this paper, we propose the architecture of modem receiver to fabricate HomePNA 2.0 chip. HomePNA suffers from inferior channel because of bridge tap, the effect of amateur HAM band and so on. To transfer data over such channel, HomePNA 2.0 uses training sequence to equalize channel and uses FD-QAM optionally as modulation method. So modem receiver demodulate QAM based signal and needs optimum architecture that fully uses these transmission feature. As a result of research, we define 2 mode function of modem receiver depending on TX/RX state. In this paper, particularly, we show the algorithm of equalizer, carrier phase recovery and frame synchromzationblock and propose architecture that improve the performance of channel equalization and is stable in operation. In the end, we estimate the performance of proposed HomePNA2.0 modem receiver over HomePNA TEST LOOP using SPW program.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.28-33
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• 2007

The front-end system having a capable of 2x reading and writing of BD-R/Ra/ROM is developed. Its readability is improved by adopting 5-tap adaptive partial response maximum likelihood (PRML) with the PR(a,b,c,d,e) type channel. Due to the proposed PRML, less than $2{\times}10^{-4}$ of the bit error rate (BER) is achieved with radial and tangential tilt margin of over${\mp}0.6{\circ}$ on 25GB disc in 2x speed. The method of an optimum Power control (OPC) for stable writing of various BD-R/RE is proposed. The developed chip contains 14-million transistors in a $60mm^2$ dies, and is fabricated in $0.18-{\mu}m$ CMOS technology.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.341-344
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• 2003

There communicates using tire supersonic waves in tire underwater, that is different from tire ground that use tire propagation. Because using Law frequency to come under tire waves, bandwidth that is able to communicate is very smaller that tire mobile communication of tire ground. Also, The channel environment changes rapidly in tire shallow underwater than tire ground. Due to such a reason, data transmission technic that is able to tire maximum application to restricted bandwidth and tire signal processing technics that is able to conquer tire rapid changes of tire channel environment are being used. Algorithm is used at tire application of these technic has a lot of tire calculating quantity. So this research reveals small bulk and equal performance using one DSP chip and then implements QPSK transmitter, that uses SHARC DSP of Analog Device company, for tire underwater supersonic waves communication rapidly decrease tire calculating quantity.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.12-19
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• 2016

The monitoring system in railway is under study to forecast any derailment and accident by defect of train. Because the monitoring system is composed of wireless sensor network based on ZigBee-communication between inside and outside of train, the study for wireless channel analysis is required. Especially, if multipath delay profile exist in the channel, the equalizer and channel estimator can be required for preventing receiver performance degradation. Therefore, we analyzed the wireless channel in train environment using measured data and, proposed the channel estimation method through the characterisitic of chip code, under the consideration of the channel characteristics in train. To show the performance of proposed method, we demonstrate the performance by mean square error(MSE), computational complexity and bit error rate(BER).