• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.5
• /
• pp.777-786
• /
• 2001

In this paper, as one of countermeasure techniques for a frequency selective fading, a digital slope equalizer(DSE) for 64-QAM digital radio relay system is analyzed in terms of principle, channel modeling, and digital implementation. Also computer simulations have been performed for DSE with a complex 13-tap adaptive time domain equalizer chip. It is shown that about 4.5 dB improvement in system signature can be obtained at the channel edge, and a variety of simulated results are reviewed in view of DSE modeling limit, operating frequency, control coefficient, signal constellation, and system signature. Finally, the functions of DSE chip confirmed up to 61 MHz clock operation are illustrated.

• Journal of Korea Multimedia Society
• /
• v.10 no.12
• /
• pp.1585-1590
• /
• 2007

This paper introduces adaptive PRML (Partial Response Maximum Likelihood) architecture with PR (a,b,c,d,e) channel type for the improved readability of high-density optical discs with capacity greater than 30GB. The proposed PRML architecture consists of an adaptive equalizer, a Viterbi detector and a channel identifier. Detailed description for each component is included. The architecture is implemented in chip and also confirmed its performance on the test board mounting the chip. Test results show that the proposed 5-tap PRML architecture is well operated, and less than $2{\times}10^{-4}$ of BER (Bit Error Rate) is achieved with radial and tangential tilt margin of ${\pm}0.6^{\circ}$ on self-made 30GB BD at 1x speed.

• Journal of Broadcast Engineering
• /
• v.11 no.3 s.32
• /
• pp.302-310
• /
• 2006

ITU-R B.O. 1130-4 Digital System E adopted for Korean satellite DMB service is a multimedia broadcasting system based on DS-CDM-QPSK technique which broadcasts audio and video contents via the satellite or terrestrial gap-filler. However, Digital System E can not provide full loading services because the multi-channel interference (MCI) is increased due to the loss of orthogonality between signature waveforms in multipath fading channels. In this paper a chip equalizer using tap selection algorithm that enhances the receiving performance is proposed and compared to the conventional rake receiver for the satellite DMB system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.119-124
• /
• 2008

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.238-241
• /
• 2000

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.

• Journal of the Semiconductor & Display Technology
• /
• v.23 no.1
• /
• pp.25-35
• /
• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.5C
• /
• pp.329-337
• /
• 2005

In this paper, we propose a new type of RAKE receiver for complementary code keying (CCK) codes, which is suitable for the multipath channel with large delay spread. Our proposed system is based on channel matched filter (CMF) with decision feedback equalizer (DFE) and contains codeword DFE structure. In our system, inter chip interference (ICI) and inter symbol interference (ISI) generated due to multipath environments are calculated by using detected CCK codeword. Also it uses the error correcting capability of CCK codes, and it can remove ISI and ICI at the same time.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.1
• /
• pp.97-103
• /
• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.5
• /
• pp.344-352
• /
• 2020

Covertness and performance are very important design goals in the underwater communications. To satisfy both of them, we proposed efficient underwater communication model which combined multiband and direct sequence spread spectrum method in order to improve performance and covertness simultaneously. Turbo coding method with 1/3 coding rates is used for channel coding algorithm, and turbo equalization method which iterately exchange probabilistic information between equalizer and decoder is used for receiver side. After optimal threshold value was set in Rake processing, this paper analyzed the performance by varying the number of chips were 8, 16, 32 and the number of bands were from 1 to 4. Through the simulation results, we confirmed that the performance improvement was obtained by increasing the number of bands and chips. 2~3 dB of performance gain was obtained when the number of chips were increased in same number of bands.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1125-1128
• /
• 1998

A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.