• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Journal of Digital Convergence
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• v.14 no.4
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• pp.419-424
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• 2016

In this paper, we studied a light distribution for the LED chips arrangement using an optical design software. The structures of the edge type LED luminaires are reflector plane, LGP(lighting guide plane) and diffuse plane. The reflector plane is on the middle of the overall structure. We had simulation that placing LED chips on the reflector center of the reflector edge by changing the position of LED chips above the reflector center at 1mm, 2mm, and 3mm respectively. In the case, when LED chips are on the center of the reflector, it shows the light distribution of the general diffuse illumination, the semi-direct distribution with 0.56 efficiency and the direct distribution with 0.31 efficiency. And the wedge type LGP shows more efficiency than the flat type. Gradually increasing shape of semi-spherical type by 0.015mm has power of 1.02W, efficiency of 0.25, and maximum luminous intensity of 0.104W/sr, it also and shows the better optical characteristics than the reflector plane that have no patterns. This semi-spherical type shows the better optical characteristics than the reflector plane that have no patterns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.716-722
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• 2017

In this paper, a fully printed NFC tag operating at 13.56 MHz was designed and fabricated using silver nano-paste and carbon ink. The proposed NFC tag has a printed coil with an inductance of $2.74{\mu}H$ on a PI film for application to an NFC tag IC with an internal capacitance of 50 pF. Screen printing technology used in this paper has advantages such as large area printing for mass production, low cost and eco-friendly process compared to conventional PCB manufacturing process. The proposed structure consists of a circular coil implemented as a single layer using silver nano-paste and carbon ink, a jumper pattern for chip mounting between the outer edge and the center of the coil, and an insulation pattern between the coil and the jumper pattern. In order to verify the performance of the proposed NFC tag, we performed the measurements of the printing line width, thickness, line resistance, adhesion and environmental reliability, and confirmed the suitability of the NFC tag based on the full-printed manufacturing method.

• Journal of the Korea Society of Computer and Information
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• v.17 no.4
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• pp.1-9
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• 2012

As we are turnning into the aged society, accidents by falling down are increasing in the aged people's group. In this paper, we design the system with the 3-Axis acceleration sensor which is composed by a single chip. The body activity signal is measured with the signal detector and RF communicator in this proposed system and the and falling by the entering signal pattern analysis with 3-Axis acceleration sensor. For the RF communication, we are using nRF24L01p and 8bits ATmega uC for the processor. The error of energy expenditure estimation between motor driven treadmill and proposed a body activity module was 7.8% respectively. Human activities and falling is monitored according to analyze and judge the critical value of the Signal Vector. as falled down if they don't turn off the alarm after specific period and the aged person's after falling down activities are their position and more.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Korean Journal of Optics and Photonics
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• v.6 no.3
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• pp.188-200
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• 1995

A design of unit magnification 2-mirror system with high resolution is presented. It is for soft X-ray(wavelength of 13 nm) projection imaging and suitable for preparation of high density semiconductor chip. In general, a holosymmetric system with unit magnification has the advantage that both coma and distortion are completely eliminated. In our holosymmetric 2-mirror system, spherical aberration is addtionally removed by using two identical paraboloidal mirror surfaces and field curvature aberration is also corrected by balancing Petzval sum and astigmatism which depends on the distance between two mirrors, so that the system is a aplanatic flat-field paraboloidal 2-mirror holosymmetric system. This 2-mirror system is small in size, and has a simple configuration with rotational symmetry about optical axis, and has also small central obscuration. Residual finite aberrations, spot diagrams, and diffraction-based MTF's are analyzed for the check of performances as soft X-ray lithography projection system. As a result, the image sizes for the resolutions of$0.25\mum$and $0.18\mum$are 4.0 mm, 2.5 mm respectively, and depths of focus for those are $2.5\mum$, $2.4\mum$respectively. This system should be useful in the fabrication of 256 Mega DRAM or 1 Giga DRAM. DRAM.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.444-447
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• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.345-352
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• 2017

In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.

• Journal of Sensor Science and Technology
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• v.6 no.5
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• pp.385-391
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• 1997

An objection of this study is to develop a measuring circuit of a gauge using radioisotope for compaction control. The gauge developed in this study makes use of radioisotope with the activity exempted from domestic atomic law and consists of measuring circuits for gamma-rays and thermal neutrons, a high voltage supply unit, and a microprocessor. To obtain meaningful numbers of pulse counts, parallel five and two circuits are provided for gamma-rays and thermal neutrons, respectively. Being simple in electrical characteristics of G-M detector for gamma-rays, pulses are counted through only a shaping circuit. Very small pulses generated from He- 3 proportional detector for thermal neutrons are amplified to the maximum of 50 [dB] and a window comparator accepts only pulses with meaning. To minimize effects of natural environmental radiation and electrical noise, circuits are electrostatically shielded and pulses made by ripples are eliminated by taking frequency of high voltage supplied to the circuit and pulse height of ripples into consideration. One-chip microprocessor is applied to process various counts, results are stored and the gauage is made capable to communicate with PC. Enough and meaningful numbers of pulses are counted with the prototype gauage for compaction control.