• Title/Summary/Keyword: Check node

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Control Frame Design for Improvement Transmit Efficiency in the Wireless Networks (무선 네트워크에서 전송효율증대를 위한 제어프레임 설계)

  • Han, Jae-Kyun;Pyeon, Seok-Beom
    • 전자공학회논문지 IE
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    • v.48 no.2
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    • pp.61-70
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    • 2011
  • IEEE 802.11 wireless network supports control frames like RTS/CTS(Request To Send / Clear To Send). Because they is defend to frame collection problems. It helps to solve the frame collection problem but decreases the throughput rate. Also, control frame makes False Node Problem. This problem is makes to other wireless nodes don't work and don't find channels in the same cell and near cells. We proposed a reformed new control frame for efficiency throughput rate and solution of False Node Problem. New control frame is to have added to 4 bytes of channel detection ability at the RTS frames. Channel detection ability supported to check channel at the wireless node start to transmit data frame, We expect that channel detection ability make prevent False Node Problem for increase to access number to channel. We perform comparative analysis in terms of delay(sec) and load(bits/sec) with reform RTS/CTS method which proves the efficiency of the proposed method.

Design of High Speed LDPC Encoder Based on DVB-S2 Standard (DVB-S2 기반 고속 LDPC 부호기 설계)

  • Park, Gun Yeol;Lee, Seong Ro;Jeon, Sung Min;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.2
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    • pp.196-201
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    • 2013
  • In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

8.1 Gbps High-Throughput and Multi-Mode QC-LDPC Decoder based on Fully Parallel Structure (전 병렬구조 기반 8.1 Gbps 고속 및 다중 모드 QC-LDPC 복호기)

  • Jung, Yongmin;Jung, Yunho;Lee, Seongjoo;Kim, Jaeseok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.78-89
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    • 2013
  • This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

Implementation of LDPC Decoder using High-speed Algorithms in Standard of Wireless LAN (무선 랜 규격에서의 고속 알고리즘을 이용한 LDPC 복호기 구현)

  • Kim, Chul-Seung;Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2783-2790
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    • 2010
  • In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

Multiple Node Flip Fast-SSC Decoding Algorithm for Polar Codes Based on Node Reliability

  • Rui, Guo;Pei, Yang;Na, Ying;Lixin, Wang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.16 no.2
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    • pp.658-675
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    • 2022
  • This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code. Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed. Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip). Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flip-ω) by considering dynamic update to measure node reliability, where ω is the order of flip-nodes set. The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region. Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions. Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (s=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).

Design and Implementation of ubiquitous blood pressure measurement system (유비쿼터스 혈압 측정 시스템의 설계 및 구현)

  • Kim, Jeong-Won
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.6 s.44
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    • pp.143-150
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    • 2006
  • In this paper, we have implemented a ubiquitous healthcare system that can measure and check the blood pressure of human in anytime and anywhere. The implemented prototype are composed of blood pressure measurement terminal, data gathering base node, and medial information server. The implemented node constructs a sensor network using the Zigbee protocol and is ported the TinyOS. The data gathering base node is linux-based node that can transfer a sensed medial data through wireless LAN. And, the medical information server stores the processed medical data and can promptly notify the urgent status to the connected medical team. Through experiment, we confirmed the possibility of ubiquitous healthcare system based on sensor network using the Zigbee.

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Rule-Based Anomaly Detection Technique Using Roaming Honeypots for Wireless Sensor Networks

  • Gowri, Muthukrishnan;Paramasivan, Balasubramanian
    • ETRI Journal
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    • v.38 no.6
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    • pp.1145-1152
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    • 2016
  • Because the nodes in a wireless sensor network (WSN) are mobile and the network is highly dynamic, monitoring every node at all times is impractical. As a result, an intruder can attack the network easily, thus impairing the system. Hence, detecting anomalies in the network is very essential for handling efficient and safe communication. To overcome these issues, in this paper, we propose a rule-based anomaly detection technique using roaming honeypots. Initially, the honeypots are deployed in such a way that all nodes in the network are covered by at least one honeypot. Honeypots check every new connection by letting the centralized administrator collect the information regarding the new connection by slowing down the communication with the new node. Certain predefined rules are applied on the new node to make a decision regarding the anomality of the node. When the timer value of each honeypot expires, other sensor nodes are appointed as honeypots. Owing to this honeypot rotation, the intruder will not be able to track a honeypot to impair the network. Simulation results show that this technique can efficiently handle the anomaly detection in a WSN.

Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

Ultimate Fracture Strength Analysis of Initially Cracked Plate (초기균열을 가진 판의 최종파괴 강도해석)

  • 백점기;서흥원
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 1991.10a
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    • pp.133-138
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    • 1991
  • The aim of the present paper is to develop a computer program predicting ultimate fracture strength of initially cracked structure under monotonically increasing external loads. For this purpose, two kinds of 3-D isoparametric solid elements, one 6-node wedge element and another 8-node brick element are formulated along the small deformation theory. Plasticity in the element is checked using von Mises' yield criterion. Elasto-plastic stiffness matrix of the element is calculated taking account of strain hardening effect. If the principal strain at crack tip which is one nodal point exceeds the critical strain dependin on the material property, crack tip is supposed to be opened and the crack tip node which was previously constrained in the direction perpendicular to the crack line is released. After that, the crack lay be propagated to the adjacent node. Once a crack tip node is fractured, the energy of the newly fractured node should be released which is to be absorbed by the remaining part. The accumulated reaction force which was carried by the newly fractured node so far is then applied in the opposite direction. During the action of crack tip relief force, since unloading may be occured in the plastic element, unloading check should be made. If a plastic element unloads, elastic stress-strain equation is used in the calculation of the stiffness matrix of the element, while for a loading element, elasto-plastic stress-strain equation is continuously used. Verification of the computer program is made comparing with the experimental results for center cracked panel subjected to uniform tensile load. Also some factors affecting ultimate fracture strength of initially cracked plate are investigated. It is concluded that the computer program developed here gives an accurate solution and becomes useful tool for predicting ultimate fracture load of initially cracked structural system under monotonically increasing external loads.

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Based on MQTT and Node-RED Implementation of a Smart Farm System that stores MongoDB (MQTT와 Node-RED를 기반한 MongoDB로 저장 하는 스마트 팜 시스템 구현)

  • Hong-Jin Park
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.5
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    • pp.256-264
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    • 2023
  • Smart farm technology using IoT is one of the technologies that can increase productivity and improve the quality of agricultural products in agriculture, which is facing difficulties due to the decline in rural population, lack of rural manpower due to aging, and increase in diseases and pests due to climate change. . Smart farms using existing IoT simply monitor farms, implement smart plant growers, and have automatic greenhouse opening and closing systems. This paper implements a smart farm system based on MQTT, an industry standard protocol for the Internet of Things, and Node-RED, a representative development middleware for the Internet of Things. First, data is extracted from Arduino sensors, and data is collected and transmitted from IoT devices using the MQTT protocol. Then, Node-RED is used to process MQTT messages and store the sensing data in real time in MongoDB, a representative NoSQL, to store the data. Through this smart farm system, farm managers can use a computer or mobile phone to check sensing information on the smart farm in real time, anytime, anywhere, without restrictions on time and space.