• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.127-128
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• 2008

The electrical characteristics of VARIOT (variable oxide thickness) with various $HfO_2$ thicknesses on thin $SiO_2$ or $Al_2O_3$ layer were investigated. Especially, the charge trapping characteristics of $HfO_2$ layer were intensively studied. The thin $HfO_2$ layer has small charge trapping characteristics while the thick $HfO_2$ layer has large memory window. Therefore, the $HfO_2$ layer is superior material and can be applied to charge storage as well as tunneling barrier of the non-volatile memory applications.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.254.2-254.2
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• 2014

The Transmission Fourier Transform Infrared spectroscopy (FTIR) of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000~2300 cm-1. It indicated that the existence of many silicon phases and defect sources in the matrix of the SiOx films. The total hysteresis width is the sum of the flat band voltage shift (${\Delta}VFB$) due to electron and hole charging. At the range voltage sweep of ${\pm}15V$, the ${\Delta}VFB$ values increase of 0.57 V, 1.71 V, and 13.56 V with 1/2, 2/1, and 6/1 samples, respectively. When we increase the gas ratio of SiH4/N2O, a lot of defects appeared in charge storage layer, more electrons and holes are charged and the memory window also increases. The best retention are obtained at sample with the ratio SiH4/N2O=6/1 with 82.31% (3.49V) after 103s and 70.75% after 10 years. The high charge storage in 6/1 device could arise from the large amount of silicon phases and defect sources in the storage material with SiOx material. Therefore, in the programming/erasing (P/E) process, the Si-rich SiOx charge-trapping layer with SiH4/N2O gas flow ratio=6/1 easily grasps electrons and holds them, and hence, increases the P/E speed and the memory window. This is very useful for a trapping layer, especially in the low-voltage operation of non-volatile memory devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.372-372
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• 2014

반도체 검출기는 입사되는 X선 에너지에 의하여 이온화되어 발생하는 전자 전공쌍을 수집함으로 방사선 정보를 확인하는 선량계로써 많은 연구와 활용이 이루어지고 있다. 하지만, X선 에너지에 의하여 반도체 검출기에서 발생하는 전기적 신호량이 높지 않기 때문에 누설 전류의 저감이 필수적이다. 누설 전류를 저감시키기 위한 방안으로 반도체 층과 전극 층의 Schottky Contact 구조의 설계, Insulating Layer의 사용, 높은 비저항의 반도체 물질 연구 등이 이루어지고 있다. 하지만, 기존에 누설 전류 저감을 위하여 Insulating Layer를 전극층과 반도체 층 사이에 형성하는 연구에 있어서 Insulating Layer와 반도체 층의 계면 사이에서 발생하는 Charge Trapping으로 인하여 생성되는 신호의 Reproducibility 저하, 동영상 적용의 제한 등의 문제점을 겪어왔다. 이에 본 논문에서는 누설 전류를 저감시킴과 동시에 Charge Trapping의 최소화를 이루기 위하여 Insulating Layer의 두께 최적화 연구를 수행하였다. 본 연구에서 사용한 Insulating Layer는 검출기 표면에 입사하는 X선 정보 손실을 최소화 시키는 동시에 누설 전류와 Charge Trapping을 최소화 시키는 방법으로써 CVD방법으로 검출기 표면에 균일하게 Insulating Layer를 코팅하였다. Insulating 물질은 Parylene을 사용하였으며, 그 중 온도, 습도 등 외부환경에 영향을 적게 받는 type C를 사용하였다. 증착에 사용한 장비의 진공도는 Torr로 설정하여 증착되는 Parylene의 두께가 약 $0.3{\mu}m$가 되게 하였으며, 실험에는 반도체 물질 PbO를 사용하였다. Parylene의 절연 특성은 Dark Current와 Sensitivity를 측정한 SNR을 이용하여 Parylene코팅이 되지 않은 동일 반도체 검출기와의 신호를 비교하였으며 또한 Parylene를 다층 제작한 검출기의 수집 신호량을 비교하였다. 제작한 검출기의 X선 조사 시의 수집 전하량 측정 결과, 100 kVp, 100mA, 0.03s의 X선 조건에서 $1V/{\mu}m$의 기준 시, Parylene를 코팅하지 않은 PbO 검출기의 Dark current는 0.0501 nA/cm2, Sensitivity는 0.6422 nC/mR-cm2, SNR은 12.184이었으며, Parylene단층의 두께인 $0.3{\mu}m$로 증착된 시편의 Dark current는 0.04097 nA/cm2, Sensitivity는 0.53732 nC/mR-cm2으로 Dark current가 감소되고 sensitivity도 감소하였지만 SNR은 13.1150으로 높아진 것을 확인할 수 있었다. Perylene이 $0.6{\mu}m$로 증착된 시편의 경우, Dark Current는 0.04064 nA/cm2, Sensitivity는 0.31473 nC/mR-cm2, SNR은 7.7443으로써 Insulating Layer가 없는 시편보다 SNR이 약 40% 낮아진 것을 확인할 수 있었다. Parylene이 $0.9{\mu}m$로 증착된 시편의 경우 Dark current는 0.0378 nA/cm2, Sensitivity 0.0461 nC/mR-cm2로 Insulating Layer가 없는 시편에 비해 SNR은 약 1/12배 감소한 1.2196이었고, Parylene이 $1.2{\mu}m$로 증착된 시편의 SNR은 1.1252로서 더 감소하였다. 따라서 Parylene을 다층 코팅한 검출기일수록 절연 효과의 영향이 커짐으로써 SNR 비교 시 수집되는 신호량이 줄어드는 것을 확인하였다. 반도체 검출기의 누설 전류를 저감시킴과 동시에 신호 수집율에 영향을 최소화시키기 위하여 Insulating Layer의 두께를 적절하게 설정하여 적용하면 Insulating Layer가 없는 검출기에 비해 누설전류를 최소한으로 줄일 수 있고 신호 검출효율이 감소하는 것을 방지할 수 있을 것이라 사료된다.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.301-305
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• 2009

Pt nanoparticles with a narrow size distribution (dia. ~4 nm) were synthesized via an alcohol reduction method and used for the fabrication of hybrid Pt-$SiO_2$ nanoparticles. Also, the self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. In addition, it was tried to show the control of thin-film thickness of hybrid Pt-$SiO_2$ nanoparticles indicating the possibility of much applications for the MOS type memory devices.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].