• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.411-414
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• 1999

70 ${\AA}$-thick oxides nitridied at various conditions were reoxidized at pemperatures of 900$^{\circ}C$ in dry-O$_2$ ambients for 5～40 mininutes. The gate oxide interface porperties as well as the oxide substrate interface properties of MOS(Metal Oxide Semiconductor) capacitors with various nitridation conditions, reoxidation conditions and pure oxidation condition were investigated. We stuided I$\sub$g/-V$\sub$g/ characteristics, $\Delta$V$\sub$g/ shift under constant current stress from electrical characteristics point of view and breakdown voltage from leakage current point of view of MOS capacitors with SiO$_2$, NO, RNO dielectrics. Overall, our experimental results show that reoxidized nitrided oxides show inproved charge trapping porperites, I$\sub$g/-V$\sub$g/ characteristics and gate $\Delta$V$\sub$g/ shift. It has also been shown that reoxidized nitridied oxide's leakage currented voltage is better than pure oxide's or nitrided oxide's from leakage current(1${\mu}$A) point of view.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.83-86
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• 1989

Electrical conductivity, I - V and DLTS have been measured on polycrystalline samples of $\alpha-Fe_{2}O_{3}$ containing small deviation from stoichiometry and small amounts of added titanium. DLTS (Deep Level Transient Spectroscopy) in the current transient mode has been applied to the measurement of the trap density at the grain boundary. Titanium enters the $\alpha-Fe_{2}O_{3}$ lattice substitutionally as $Ti^{4+}$, thus producing an $Fe^{2+}$ and maintaining the average charge per cation at three. The $Fe^{2+}$acts as a donor center with respect to the surrounding $Fe^{3+}$ions.

• Journal of IKEEE
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• v.17 no.3
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• pp.229-233
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• 2013

We investigated electrical conduction and resistance switching behavior of the Ag/ZnO/Ti structures for random access memory devices. These films were prepared on glass substrate by dc sputtering technique at room temperature. The resistance switching follows unipolar switching mode with small switching voltages (0.4 V - 0.6 V). Two electrical conduction mechanisms dominating the LRS and HRS are Ohmic and trap-controlled space charge limited current, respectively. These both conductions are consistent with the filamentary model. Based on the filamentary model, the switching mechanism was also interpreted.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.200-200
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• 2010

이 논문에서는 field-effect mobility를 향상시키기 위해 triple-layer (SiNx/SiO2/SiOxNy stack 구조)를 gate dielectric material 로 LTPS TFTs에 적용하였다. 이는 플라즈마 처리 기법과 적층구조의 효과적인 in-situ 공정을 이용하여 interface trap과 mobile charge를 낮추어 높은 이동도의 결과를 생각하고 실험하였다. 실험은 SiO2 gatedielectric과 triple-gate dielectric의 C-V curve를 1 MHz의 주파수에서 측정하였다. 또한 Transfer characteristics를 single SiO2 gatedielectric과 triple-gate dielectric of SiNx/SiO2/SiOxNy를 STA 장비를 이용해 측정하였다. 위의 측정을 통해 threshold voltage, mobility, subtheshold swing, driving current, ON/OFF current ratio를 비교 분석하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.37-38
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• 2000

The ZnS:Tb thin-film electroluminescent devices were grown by atomic layer deposition with utilizing single-layer aluminum oxide and/or multilayered tantalum aluminum oxide, $Ta_xAl_yO$, as upper and lower insulating layers. These devices were investigated in terms of the luminescent and electrical characteristics. From this analysis, the devices using the $Ta_xAl_yO$ instead of $Al_2O_3$ were observed to have a lower threshold voltage for emission due to the higher relative dielectric constant of $Ta_xAl_yO$ insulators than that of the $Al_2O_3$ device. And there was a large amount of dynamic space charge generation in the phosphor of the device with the $Ta_xAl_yO$ insulators seemingly due to electron multiplication such as trap ionization.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.756-759
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• 2009

We described the growth of undoped ZnO thin films and their optical properties changing with a various growth temperature. The undoped ZnO thin films were grown on $c-Al_2O_3$ substrates using pulsed laser deposition (PLD) at room temperature, 200, 400, and $600^{\circ}C$, respectively. Field emission microscopy (FE-SEM) measurements showed that the grain size of undoped ZnO thin films are increasing as a increase of growth temperature. In addition, we were investigated that the structural and optical properties of undoped ZnO thin films by x-ray diffraction (XRD) and photoluminescence (PL) studied. Also, we could confirmed that the exciton luminescence was strongly related to charge trap by grain boundary of the samples using micro-PL measurement.