• 대한전자공학회논문지SD
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• 제38권9호
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• pp.634-642
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• 2001

Buried channel 도파로와 ridge 도파로에 대하여 variational method (VM)과 유효굴절율 방법을 사용하여 2차원의 필드 분포를 구한 뒤 angular spectrum 방법을 적용하여 여러 개의 도파로 두께에 대하여 도파로 폭에 따른 단면 반사율을 계산하고 이를 비교 검토하였다. 도파로 폭에 따른 단면 반사율 변화량은 buried channel 도파로의 경우는 매우 크게 나타났으나 ridge 도파로의 경우는 buried channel 도파로의 변화량에 비해 매우 작게 나타났다. Angular spectrum 방법을 사용하여 채널 도파로 소자의 단면 반사율을 계산할 때 사용되는 2차원의 필드 분포의 정확성은 반사율 값에 큰 영향을 미침을 알 수 있었다. 유효굴절율 방법의 경우 도파로 폭과 도파로 두께가 감소할수록 필드 분포의 부정확성으로 인해 정확한 반사율 값과의 오차가 심하게 나타났다. 반면에 VM을 사용하여 구한 필드 분포는 도파로 폭과 두께에 관계없이 정확한 필드 분포와 오차가 적어 유효굴절율 방법보다 정확한 반사율 값을 구할 수 있었다. 유효굴절율 방법이 잘 적용되는 영역에서는 두 방법을 사용하여 구한 반사율의 차이가 매우 작음을 알 수 있었다.

• Journal of the Optical Society of Korea
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• 제7권4호
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• pp.269-274
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• 2003

In this paper, a Gaussian apodization technique applied to a transmission volume hologram for holographic demultiplexer is proposed. The Gaussian apodized grating of 15 mm ${\times}$ 11mm size, $38{\mu}m$ thickness and 3.2 mm horizontal standard deviation of the Gaussian index modulation profile was fabricated. A 22-channel demultiplexer based on that grating has been optically demonstrated. The channel spacing, the interchannel cross-talk level and the channel uniformity of 0.8 nm, -30 dB and 1.5 dB, respectively, were obtained.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 전자공학회논문지D
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• 제34D권10호
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• pp.53-59
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• 1997

In this paper, we present a 20 GHz low-loss dual-mode channel filter designed by using mode matching method. The performance of dual-mode channel filter mainly depends on iris characteristics. Therefore the exact design of iris is the key point to get good frequncy response of the filter. MOde matching technique is widely used ot design several kinds of waveguide filters because it is simple in theory and can easily calculate the scattering matrices at the discontinuities with simple structure like iris coupled filters. Additionally the effect for finite thickness of the iris in the dual-mode cavity iflter is analyzed by te full-wave method, providing the exact filter implementation without trial and error.

• 전자공학회논문지D
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• 제34D권12호
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• pp.69-75
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• 1997

A Si-channle MESFET using .delta.-doped layers was designed and the considerable enhancement of the current driving capability of the device was observed by simulation. The channel consists of double .delta.-doped layers separated by a low-doped spacer. Cariers are spilt from the .delta.-doped layers and are accumulated in the spacer. The saturation current is enhanced by the contribution of the carriers in the spacer. Among the design parameters that affect the peformance of the device, the thickness of the spacer and the ratio of the doping concentrations of the two .delta.-doped layers were studied. The spacer thickenss of 300~500.angs. and the doping ratio of 3~4 were shown to be the optimized values. The saturation current was observed to be increased by 75% compared with a bulk-channel MESFET. The performances of transconductance, output resistance, and subthreshold swing were also enhanced.

• Advances in Computational Design
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• 제1권2호
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• pp.207-220
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• 2016

The aim of this study is to investigate the effect of stiffened element and edge stiffener in the behaviour and flexural strength of built-up cold-formed steel beams. An experimental and analytical analysis of CFS channel sections in four different geometries is conducted, including simple channel sections, a stiffened channel section with or without edge stiffeners. Nonlinear finite element models are developed using finite element analysis software package ANSYS. The FEA results are verified with the experimental results. Further, the finite element model is used for parametric studies by varying the depth, thickness, and the effect of stiffened element, edge stiffener and their interaction with compression flanges on stiffened built-up cold-formed steel beams with upright edge stiffeners. In addition, the flexural strength predicted by the finite element analysis is compared with the design flexural strength calculated by using the North American Iron and Steel Institute Specifications for cold-formed steel structures (AISI: S100-2007) and suitable suggestion is made.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.61-65
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• 2010

Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

• 대한전기학회논문지
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• 제38권6호
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.