• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

• Journal of information and communication convergence engineering
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• v.7 no.3
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• pp.361-365
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• 2009

This paper has been presented the transport characteristics of FinFET using the analytical potential model based on the Poisson's equation in subthreshold and threshold region. The threshold voltage is the most important factor of device design since threshold voltage decides ON/OFF of transistor. We have investigated the variations of threshold voltage and drain induced barrier lowing according to the variation of geometry such as the length, width and thickness of channel. The analytical potential model derived from the three dimensional Poisson's equation has been used since the channel electrostatics under threshold and subthreshold region is governed by the Poisson's equation. The appropriate boundary conditions for source/drain and gates has been also used to solve analytically the three dimensional Poisson's equation. Since the model is validated by comparing with the three dimensional numerical simulation, the subthreshold current is derived from this potential model. The threshold voltage is obtained from calculating the front gate bias when the drain current is $10^{-6}A$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1033-1041
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• 1990

In this paper, under pinch-off conditions, the gate-drain breakdown voltage characteristics of GaAs Power MESFET's as a function of device parameters such as channel thickness, doping concentration, gate length etc. are analyzed. Using the Green's function, the gate ionic charge induced by the depleted channel ionic charge is calculated. The impact ionization integral by avalanche multiplication between gate and drain is used to investigate breakdown phenomena. Especially, the localized excess surface charge effect as well as the uniform surface charge effect on breakdown voltage is considered.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.250-250
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• 2010

The random telegraph signal (RTS) for the NOR flash cell scaling is investigated. An innovative method to suppress the RTS, based on the device engineering, is proposed. By optimizing the channel doping profile and using the high-k tunnel dielectric, it is confirmed from three-dimensional (3-D) simulation, that the $V_{th}$ amplitude, dueto RTS, is significantly suppressed, from approximately 0.5 to 0.07 V in the middle of the channel at 45 nm NOR Flash technology. From this result, it is expected that the proposed method to suppress the RTS amplitude is essential for further cell size scaling in Flash memory.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1373-1379
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• 1988

This paper describes a two-dimensional analysis of the potential distribution and electron concentration of the MODFET at channel using FDM. More exact analysis can be obtained by two-dimensional analysis which considers parasitic effects ignored in one-dimensional analysis. Using Poisson and Shrodinger equations, the potential distribution and the wave function are calculated within a constant error bound. As a result, the relations between the thickness of spacer, doping concentration of (n) AlGaAs layer, and the sheet density of the 2DEG (2 Dimensional Electron Gas) of MODFET at channel are suggested quantitively. The sheet density of the 2DEG is increased as the thickness of the spacer is decreased of the doping concentration of the (n)AlGaAs layer is lowered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.110-110
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• 2010

현재 박막 트랜지스터는 비정질 실리콘 기반의 개발이 주를 이루고 있으며, 이 비정질 실리콘은 성막공정이 간단하고 대면적에 용이하지만 전기적인 특성이 우수하지 않기 때문에 디스플레이의 적용에 어려움을 겪고 있다. 이에 따라 poly-Si을 이용한 박막 트랜지스터의 연구가 진행되고 있는데, 이는 공정온도가 높고, 대면적에의 응용이 어렵다. 따라서 앞으로 저온 공정이 가능하며 대면적 응용이 용이한 박막 트랜지스터의 연구가 필수적이다. 한편 최근 박막 트랜지스터의 채널층으로 사용되는 물질에는 oxide 기반의 ZnO, SnO2, In2O3 등이 주로 사용되고 있고, 보다 적합한 채널층을 찾기 위한 연구가 많이 진행되어 왔다. 최근 Hosono 연구팀에서 IGZO를 채널층으로 사용하여 high mobility, 우수한 on/off ratio의 특성을 가진 소자 제작에 성공함으로써 이를 시작으로 IGZO의 연구 또한 세계적으로 활발한 연구가 이루어지고 있다. 특히, ZnO는 wide band gap (3.37eV)을 가지고 있어 적외선 및 가시광선의 투과율이 좋고, 전기 전도성과 플라즈마에 대한 내구성이 우수하며, 낮은 온도에서도 성막이 가능하다는 특징을 가지고 있다. 그러나 intrinsic ZnO 박막은 bias stress 같은 외부 환경이 변했을 경우 전기적인 성질의 변화를 가져올 뿐만 아니라 고온에서의 공정이 불안정하다는 요인을 가지고 있다. ZnO의 전기적인 특성을 개선하기 위해 본 연구에서는 hafnium을 doping한 ZnO을 channel layer로 소자를 제작하고 전기적 특성을 평가하였다. 이를 위해 DC magnetron sputtering을 이용하여 ZnO 기반의 박막 트랜지스터를 제작하였다. Staggered bottom gate 구조로 ITO 물질을 전극으로 사용하였으며, 제작된 소자는 semiconductor analyzer를 이용하여 출력특성과 전이 특성을 평가하였으며, ZnO channel layer 증착시 hafnium이 도핑 되는 양을 조절하여 소자를 제작한 후 intrinsic ZnO의 소자 특성과 비교 분석하였다. 그 결과 hafnium을 doping 시킨 소자의 field effect mobility가 $6.42cm^2/Vs$에서 $3.59cm^2/Vs$로 낮아졌지만, subthreshold swing 측면에서는 1.464V/decade에서 0.581V/decade로 intrinsic ZnO 보다 좋은 특성을 나타냄을 알 수 있었다. 그리고 intrinsic ZnO의 경우 외부환경에 대한 안정성 문제가 대두되고 있는데, hafnium을 도핑한 ZnO의 경우 temperature, bias temperature stability, 경시변화 등의 다양한 조건에서의 안정성이 확보된다면 intrinsic ZnO 박막트랜지스터의 문제점을 해결할 수 있는 물질로 될 것이라고 기대된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.691-694
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as charge distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.