• Journal of Navigation and Port Research
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• v.39 no.4
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• pp.293-297
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• 2015

Underwater acoustic communications has been limited use for military purposes in the past. However, the fields of underwater applications expend to detection, submarine and communication in recent. The excessive multipath encountered in underwater acoustic communication channel is creating inter symbol interference, which is limiting factor to achieve a high data rate and bit error rate performance. To improve the performance of a received signal in underwater communication, many researchers have been studied for channel coding scheme with excellent performance at low SNR. In this paper, we applied BCJR decoder based ( 2,1,7 ) convolution codes and to compensate for the distorted data induced by the multipath, we applying the turbo equalization method. Through the underwater experiment on the Gyeungcheun lake located in Mungyeng city, we confirmed that turbo equalization structure of BCJR has better performance than hard decision and soft decision of Viterbi decoding. We also confirmed that the error rate of decoder input is less than error rate of $10^{-1}$, all the data is decoded. We achieved sucess rate of 83% through the experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1026-1037
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• 2016

3rd Generation Partnership Project (3GPP) is the progressing standardization of the narrowband IoT (NB-IoT) system to support massive devices for the Internet of Things (IoT) services. The NB-IoT system uses a coverage class technique to increase the performance of the NB-IoT system while serving massive devices in very wide coverage area. A moving device can change the coverage class according to the distance or the channel state between the base station and the moving device. However, in the conventional NB-IoT standard, the performance of the NB-IoT system degrades because the coverage class is changed based on the fixed criterion. This paper proposes the coverage class adaptation schemes to increase the performance of the NB-IoT system by dynamically change the coverage class according to the location or the channel state of the device. Simulation results show that the proposed coverage class adaptation scheme decreases both the signaling overhead and the PDCCH decoding error rate in comparison with the conventional coverage class adaptation scheme in the 3GPP standard.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.48-52
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• 2007

Recently, the research of GPS receiver which uses the Software-Defined Radio(SDR) technique is being actively proceeded instead of traditional hardware-based receiver. The software-based GPS receiver indicates that the signal acquisition and tracking treated by the hardware-based platform are processed as the software technique through a microprocessor. In this paper, GPS software receiver is designed by using SDR technique and then the signal acquisition, tracking, and the navigation message decoding parts are verified through the PC-based simulation. Moreover, the efficient algorithms are developed about the signal acquisition and tracking parts in order to obtain the accurate pseudorange. Finally, the pseudorange is calculated through the relative channel delay received through the different satellite of L1 frequency band. GPS software receiver proposed in this paper will be included in the element of GPS/Galileo complex system of development target and will provide not only the method that verifies the performance for Galileo Sensor Station standard but also usability by providing various debugging environments.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.