• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.7
• /
• pp.782-787
• /
• 2004

Superconducting flux flow transistor (SFFT) is based on a control of the Abrikosov vortex flowing along a channel. The induced voltage by moving of the Abrikosov vortex in an SFFT is greatly affected by the thickness, the width, and the length of channel. In order to fabricate a reproducible channel in the SFFT, we studied the variation of the critical characteristics of ${YBa}_2{Cu}_3{O}_7-\delta(YBCO)$ thin films with the etching time using ICP (Inductively coupled plasma) system. From the simulation, it was certified that the vortex velocity was increased in a low pinning energy at channel width 0,5 mm. The surfaces of YBCO thin film were etched by ICP etching system. We observed the etched channel surfaces by AFM (Atomic Force Microscope) and measured the critical current density with etching time. As a measured results, the etching thickness of channel should be optimized to fabricated a flux flow transistor with specified characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.11a
• /
• pp.259-262
• /
• 2003

Superconducting flux flow transistor(SFFT) is based on a control of the Abrikosov vortex flowing along a channel. The induced voltage by moving of the Abrikosov vortex in SFFT is greatly affected by the thickness and width, of channel. In order to fabricate a reproducibility channel in SFFT, we have researched the variation of the critical characteristics of YBCO thin films with the etching time using ICP(Inductively coupled plasma) system. It was certified that the velocity of vortex decreased with increasing the width of channel and was saturated faster in low bias from a simulation. An etching mechanism of YBCO thin films by ICP system was also certified by AFM(Atomic Force Microscope) and by measuring the critical current density with etching time. As measurement result, we could analyze that we should optimize the etching thickness of channel part to construct a flux flow transistor with desired characteristics.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.1500-1503
• /
• 1997

In this paper a multiple channel EPD controller is developed which enables us to detect endpoints simultaneously in the plasma etching process operated in multiple etching chambers and its performance characteristic are investigated. for the accurate detectiion of endpoint the developed EDP controller was able to implement endpoint detectiions by integrating the existing EPD controllers with the techiques of artificial intellignet, to enhance its performance. The performance of the developed EPD controller was carried out by repeated experiments of endpoint detection in the acrual production line of semiconductor manufacturing. It's utility for endpoint detectiion was accurately evaluated in various etching process. The control capability of multiple etching chambers enhances its application compared with the existing one, and also increases the user utility os that the efficiency of operation was improved.

• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.23-27
• /
• 2009

Ohmic contact formation and etching processes for the fabrication of MBE (molecular beam epitaxy) grown GaSb-based p-channel HEMT devices on Si substrate have been studied. Firstly, mesa etching process was established for device isolation, based on both HF-based wet etching and ICP-based dry etching. Ohmic contact process for the source and drain formation was also studied based on Ge/Au/Ni/Au metal stack, which resulted in a contact resistance as low as $0.683\;{\Omega}mm$ with RTA at $320^{\circ}C$ for 60s. Finally, for gate formation of HEMT device, gate recess process was studied based on AZ300 developer and citric acid-based wet etching, in which the latter turned out to have high etching selectivity between GaSb and AlGaSb layers that were used as the cap and the barrier of the device, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.5
• /
• pp.424-428
• /
• 2003

The channel of a superconducting flux flow transistor has been fabricated with plasma etching method using a inductively coupled plasma etching. The ICP conditions then were ICP Power of 450 W, rf chuck power of 150 W, the pressure in chamber of 5 mTorr, and Ar : Cl$_2$=1:1. Especially, over the 5 mTorr, the superconducting thin films were not etched. The channel etched by plasma gas showed the critical temperature over 85 K. The critical current of the SFFT was altered by varying the external applied current. As the external applied current increased from 0 to 12 mA, the critical current decreased from 28 to 22 mA. Then the obtained trans-resistance value was smaller than 0.1 $\Omega$ at a bias current of 40 mA.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1924-1926
• /
• 2001

A novel wet release process ($\mu$ CARP - Micro Channel Assisted Release Process) for releasing an extreme large-area plate structure without etching hole is proposed and experimented. Etching holes in conventional process reduce a effective area and degrade an optical characteristics by a diffraction. In addition, as the area of a released structure increases, the stietion becomes more serious. The proposed process resolves these problems by the introduction of a micro fluidic channel beneath the structure which will be released. In this paper, a 5 mm${\times}$5mm-single crystal silicon plate structure was released by the proposed $\mu$CARP without etch holes on the structure. The variation in etching time with respect to the of the introduced micro channel is also examined. This process is expected to be beneficial for the actuator of a nano-scale data storage and the scanning mirror.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.711-714
• /
• 2004

A new design for improving the aperture ratio of bottom emission type AMOLED is investigated. In conventional, the TFT of AMOLED fabrication method is "Etch Stopper (7-mask)", so the aperture ratio is limited in 28${\sim}$33% by Cs(Storage Capacitor). A high aperture ratio TFT is designed by using BCE(Back Channel Etching 5-mask) fabrication way and the aperture ratio is up to 40% shown in 2.2"AMOLED display.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.2
• /
• pp.152-155
• /
• 2011

Even though nano-scale materials were very advantageous for various applications, there are still problems to be solved such as the stabilization of surface state and realization of low contact resistances between a semiconducting nanowire and electrodes in nano-electronics. It is well known that the effects of contacts barrier between nano-channel and metal electrodes were dominant in carrier transportation in individual nano-electronics. In this report, it was investigated the electrical properties of GaN nanorod devices after chemical etching and rapid thermal annealing for making good contacts. After KOH wet-etching of the contact area the devices showed better electrical performance compared with non-treated GaN individual devices but still didn't have linear voltage-current characteristics. The shape of voltage-current properties of GaN devices were improved remarkably after rapid thermal annealing as showing Ohmic behaviors with further bigger conductivities. Even though chemical etching of the nanorod surfaces could cause scattering of carriers, in here it was shown that the most important and dominant factor in carrier transport of nano-electronics was realization of low contact barrier between nano-channel and metal electrodes surely.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.74-77
• /
• 2002

The channel of the superconducting Flux Flow Transistor has been fabricated with plasma etching method using ICP. The ICP conditions were 700 W of ICP power, 150 W of rf chuck power, 5 mTorr of the pressure in chamber and 1:1 of Ar : Cl$_2$, respectively. The channel etched by plasma gas showed superconducting characteristics of over 77 K and superior surface morphology. The critical current of SFFT was altered by varying the external applied current. As the external applied current increased from 0 to 12 mA, the critical current decreased from 28 to 22 mA. Then the obtained r$\sub$m/ values were smaller than 0.1Ω at a bias current of 40 mA. The current gain was about 0.5. Output resistance was below 0.2 Ω.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2004.10a
• /
• pp.351-354
• /
• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.